tsnlab / npuLinks
☆22Updated last year
Alternatives and similar repositories for npu
Users that are interested in npu are comparing it to the libraries listed below
Sorting:
- SystemVerilog IPs and Modules for architectural redundancy designs.☆14Updated last week
- A simple, scalable, source-synchronous, all-digital DDR link☆27Updated last month
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated 2 years ago
- XDMA PCIe to DDR4 and GPIO and BRAM for the Innova-2 Flex XCKU15P FPGA☆18Updated last year
- Neural Network accelerator powered by MVUs and RISC-V.☆13Updated last year
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 8 years ago
- RISC-V soft-core PEs for TaPaSCo☆22Updated last year
- ☆16Updated 6 years ago
- APB Logic☆19Updated 7 months ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- xkDLA:XinKai Deep Learning Accelerator (RTL)☆34Updated last year
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆21Updated 2 months ago
- IP operations in verilog (simulation and implementation on ice40)☆56Updated 5 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆30Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- ☆12Updated 4 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆35Updated this week
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 9 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 5 years ago
- FIR,FFT based on Verilog☆13Updated 7 years ago
- Network on Chip for MPSoC☆26Updated last month
- Register-based and RAM-based FIFOs designed in Verilog/System Verilog.☆18Updated 11 months ago
- SystemC UVM verification environment with Constraint Randomized stimulus, Coverage, Assertions☆20Updated 7 months ago
- Theia: ray graphic processing unit☆20Updated 11 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs, with error detection capabili…☆15Updated last year
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆40Updated 2 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago
- USB -> AXI Debug Bridge☆39Updated 4 years ago
- ☆30Updated last week