☆25Jun 21, 2024Updated last year
Alternatives and similar repositories for npu
Users that are interested in npu are comparing it to the libraries listed below
Sorting:
- ☆14Apr 24, 2023Updated 2 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Feb 24, 2026Updated last week
- A hardware accelerator for General Matrix Multiply, developed in SystemC using ESP.☆16May 26, 2021Updated 4 years ago
- A 2D mesh Network on Chip with 5-stage pipelined router, all implemented in Verilog and run on Artix-7 FPGA.☆17May 30, 2023Updated 2 years ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆166Mar 5, 2025Updated 11 months ago
- A small Neural Network Processor for Edge devices.☆16Nov 22, 2022Updated 3 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆45Jun 24, 2022Updated 3 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆20May 4, 2017Updated 8 years ago
- Xilinx JTAG Toolchain on Digilent Arty board☆17Mar 15, 2018Updated 7 years ago
- Matrix Multiplication in Hardware☆16Jun 3, 2020Updated 5 years ago
- ☆24Aug 9, 2022Updated 3 years ago
- FPGA implementation of a simple scanline based 2d graphics engine☆24Feb 26, 2019Updated 7 years ago
- Theia: ray graphic processing unit☆20Jul 17, 2014Updated 11 years ago
- Cryptography accelerator ASIC (for AES128/AES256 and SHA256) using Skywater 130nm process node (main project repo). Taped out in December…☆23Jan 13, 2021Updated 5 years ago
- Open-source Neural Processing Unit (NPU) from China ❤☆37Jan 29, 2025Updated last year
- LLVM Backend tutorial Cpu0☆25Nov 5, 2023Updated 2 years ago
- ☆27Aug 2, 2021Updated 4 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆26Jan 19, 2026Updated last month
- Gowin DDR3 Controller with AXI4 Implementation | 高云DDR3内存控制器AXI4接口实现☆28Mar 3, 2024Updated 2 years ago
- Weber State University Senior Project - (Optical Frequency Domain Reflectometry)☆12Feb 28, 2024Updated 2 years ago
- Codes for femtosecond laser interaction research☆13Jun 25, 2025Updated 8 months ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Feb 1, 2020Updated 6 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆33Jun 12, 2023Updated 2 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆65Jan 13, 2021Updated 5 years ago
- 在FPGA上面实现一个NPU计算单元。能够执行矩阵运算（ADD/ADDi/ADDs/MULT/MULTi/DOT等）、图像处理运算（CONV/POOL等）、非线性映射（RELU/TANH/SIGM等）。☆293Aug 16, 2018Updated 7 years ago
- Documents for ARM☆35May 8, 2025Updated 9 months ago
- ☆32Jan 23, 2021Updated 5 years ago
- Bilinear interpolation realizes image scaling based on FPGA☆30Jul 11, 2020Updated 5 years ago
- ☆31Aug 8, 2020Updated 5 years ago
- ☆33Mar 20, 2025Updated 11 months ago
- PCIe System Verilog Verification Environment developed for PCIe course☆14Mar 26, 2024Updated last year
- A scalable Eyeriss model in SystemC.☆33Jan 1, 2023Updated 3 years ago
- Toy RISC-V LLVM backend☆30Aug 15, 2022Updated 3 years ago
- Software in MATLAB that show the link budget for free space optics communications between OGS (optical ground station) and satellite (Upl…☆10Jun 7, 2022Updated 3 years ago
- Pipelined FFT/IFFT 256 points processor☆10Jul 17, 2014Updated 11 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆34Jun 22, 2024Updated last year
- Verilog Code for a JPEG Decoder☆34Mar 7, 2018Updated 7 years ago
- ☆67May 14, 2022Updated 3 years ago
- Wrappers for open source FPU hardware implementations.☆37Nov 27, 2025Updated 3 months ago