Alternatives and similar repositories for npu:

Users that are interested in npu are comparing it to the libraries listed below

• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆20Updated 2 years ago
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆16Updated 5 years ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆29Updated 9 years ago
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆32Updated last year
• obilaniu / MVU
  Neural Network accelerator powered by MVUs and RISC-V.
  ☆13Updated 9 months ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆26Updated 3 years ago
• SeanZarzycki / openSPARC-FPU
  ASIC Design of the openSPARC Floating Point Unit
  ☆13Updated 8 years ago
• mwrnd / innova2_xcku15p_ddr4_bram_gpio
  XDMA PCIe to DDR4 and GPIO and BRAM for the Innova-2 Flex XCKU15P FPGA
  ☆18Updated last year
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆37Updated 2 years ago
• freecores / wdsp
  DSP WishBone Compatible Cores
  ☆13Updated 10 years ago
• dpretet / svlogger
  SystemVerilog Logger
  ☆17Updated 2 years ago
• mpskex / chisel-npu
  Chisel implementation of Neural Processing Unit for System on the Chip
  ☆21Updated 2 weeks ago
• PacoReinaCampo / MPSoC-NoC
  Network on Chip for MPSoC
  ☆26Updated last week
• merledu / azadi-soc
  Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.
  ☆30Updated last year
• PacoReinaCampo / SoC-RISCV
  System on Chip with RISCV-32 / RISCV-64 / RISCV-128
  ☆23Updated this week
• open-dv / dma_axi
  ☆16Updated 6 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆32Updated 2 months ago
• esa-tu-darmstadt / tapasco-riscv
  RISC-V soft-core PEs for TaPaSCo
  ☆18Updated 10 months ago
• pulp-platform / redundancy_cells
  SystemVerilog IPs and Modules for architectural redundancy designs.
  ☆13Updated this week
• pulp-platform / adv_dbg_if
  Advanced Debug Interface
  ☆14Updated 3 months ago
• pulp-platform / rbe
  Reconfigurable Binary Engine
  ☆16Updated 4 years ago
• 0ctobyte / procyon
  Procyon is the brightest star in the constellation of Canis Minor. But it's also the name of my RISC-V out-of-order processor.
  ☆12Updated 2 years ago
• pulp-platform / apb
  APB Logic
  ☆17Updated 4 months ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆31Updated 6 months ago
• jerry-D / 64-bit-Universal-Floating-Point-ISA-Compute-Engine
  RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine
  ☆22Updated 3 years ago
• FPGA-Research / eFPGA---RTL-to-GDS-with-SKY130
  This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
  ☆30Updated 3 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆65Updated 2 months ago
• pbridd / lzrw1-compression-core
  This is the repository for a verilog implementation of a lzrw1 compression core
  ☆18Updated 7 years ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆36Updated 3 years ago
• bhunt2 / DDR4Sim
  DDR4 Simulation Project in System Verilog
  ☆41Updated 10 years ago