BaoBao-zhu / RV-SCNNLinks
A Custom RISC-V Instruction Extension for SNN and CNN Computation
☆15Updated 9 months ago
Alternatives and similar repositories for RV-SCNN
Users that are interested in RV-SCNN are comparing it to the libraries listed below
Sorting:
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- Spiking Neural Network Accelerator☆15Updated 3 years ago
- SNN on FPGA☆10Updated 3 years ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆17Updated 9 months ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- ☆16Updated 3 weeks ago
- (Verilog) A simple convolution layer implementation with systolic array structure☆13Updated 3 years ago
- ☆28Updated last week
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆11Updated 4 years ago
- eyeriss-chisel3☆40Updated 3 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆27Updated last year
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆28Updated 3 years ago
- ☆19Updated 4 years ago
- Template for project1 TPU☆18Updated 4 years ago
- ☆17Updated 4 years ago
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆14Updated 10 months ago
- 关于 移植模型至gemmini的文档☆27Updated 3 years ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆34Updated 5 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆16Updated 6 years ago
- ☆47Updated last month
- This is the RTL implementation of Shenjing, a low power neuromorphic computing accelerator☆17Updated 5 years ago
- ☆33Updated 6 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆19Updated last year
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆11Updated 2 years ago
- Hardware accelerator for convolutional neural networks☆45Updated 2 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- ☆15Updated last year
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆53Updated last month
- ☆27Updated 5 years ago