BaoBao-zhu / RV-SCNNLinks
A Custom RISC-V Instruction Extension for SNN and CNN Computation
☆16Updated 11 months ago
Alternatives and similar repositories for RV-SCNN
Users that are interested in RV-SCNN are comparing it to the libraries listed below
Sorting:
- This project is to design yolo AI accelerator in verilog HDL.☆20Updated 10 months ago
- SNN on FPGA☆10Updated 3 years ago
- ☆19Updated 4 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆12Updated 4 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆30Updated last year
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆36Updated 6 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- Tensor Processing Unit implementation in Verilog☆8Updated 4 months ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆53Updated 10 months ago
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆12Updated 2 years ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆34Updated 5 years ago
- ☆47Updated 3 months ago
- ☆34Updated 6 years ago
- ☆31Updated 2 months ago
- ☆17Updated 2 months ago
- Hardware accelerator for convolutional neural networks☆47Updated 3 years ago
- eyeriss-chisel3☆41Updated 3 years ago
- EE 272B - VLSI Design Project☆13Updated 4 years ago
- Template for project1 TPU☆19Updated 4 years ago
- ☆65Updated 6 years ago
- (Verilog) A simple convolution layer implementation with systolic array structure☆13Updated 3 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆38Updated last year
- Systolic array based simple TPU for CNN on PYNQ-Z2☆34Updated 3 years ago
- HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…☆59Updated 5 months ago
- A systolic array matrix multiplier☆24Updated 5 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆10Updated 3 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆18Updated 6 years ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆21Updated 11 months ago