Alternatives and similar repositories for RV-SCNN

Users that are interested in RV-SCNN are comparing it to the libraries listed below

• HanPU-Code / CNN_YOLO_AI_accelerator
  This project is to design yolo AI accelerator in verilog HDL.
  ☆28Updated last year
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆25Updated 4 years ago
• evan199893 / TPU_systolic_array_HW_accelerator
  Tensor Processing Unit implementation in Verilog
  ☆10Updated 8 months ago
• Spiritator / FPGA_LeNet5_ws_8x8
  FPGA implement of 8x8 weight stationary systolic array DNN accelerator
  ☆16Updated 4 years ago
• KyleParkJong / Network-on-Chip-Simulator
  Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator
  ☆34Updated last year
• BoChen-Ye / Tiny_LeViT_Hardware_Accelerator
  This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.
  ☆25Updated last year
• hazooree / LeNet-CNN-Accelerator-Hardware-for-FPGA
  An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017
  ☆19Updated 6 years ago
• gem5-X / TiC-SAT
  ☆19Updated 6 months ago
• yuyuranium / FPGA-Project-2022-simple-tpu
  Systolic array based simple TPU for CNN on PYNQ-Z2
  ☆38Updated 3 years ago
• 8krisv / CNN-ACCELERATOR
  Hardware accelerator for convolutional neural networks
  ☆60Updated 3 years ago
• zli87 / Processor-and-Accelerator
  MIPS Processor, BNN Accelerator, AXI4 interface, Cache Controller and LRU replacement
  ☆13Updated 3 years ago
• AIC2021 / AIC2021_TPU_Template
  Template for project1 TPU
  ☆19Updated 4 years ago
• snagiri / CSE237D-PYNQ-SNN-Accelerator
  Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board
  ☆38Updated 6 years ago
• oshears / SNN-FPGA-Implementation
  ☆20Updated 4 years ago
• hyupupup / conv_systolic_array
  (Verilog) A simple convolution layer implementation with systolic array structure
  ☆13Updated 3 years ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆66Updated 3 weeks ago
• kuladeepsaireddy / OpenNoc
  ☆37Updated 6 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 3 years ago
• wzc810049078 / systolic-array-matrix-multiplier
  A systolic array matrix multiplier
  ☆29Updated 6 years ago
• Minz9 / SNN-on-FPGA
  SNN on FPGA
  ☆11Updated 3 years ago
• saunak1994 / CyNAPSEv11
  The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL
  ☆36Updated 6 years ago
• githubofaliyev / SNN-DSE
  Hardware and software implementation of Sparsely-active SNNs
  ☆20Updated 10 months ago
• pulp-platform / ITA
  ☆57Updated 7 months ago
• ryaanluke / DNN-Hardware-Accelerator
  SystemVerilog files for lab project on a DNN hardware accelerator
  ☆18Updated 4 years ago
• Starrynightzyq / soNN
  A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.
  ☆29Updated 4 years ago
• alexmr09 / Mixed-precision-Neural-Networks-on-RISC-V-Cores
  ☆35Updated last month
• KULeuven-MICAS / tinyvers
  TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.
  ☆20Updated 2 years ago
• Deepak42074 / SRAM_IMC_MPW8
  The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…
  ☆16Updated 2 years ago
• suchuankai / CNN-hw-accelerator
  CNN hardware accelerator to accelerate quantized LeNet-5 model
  ☆41Updated 2 years ago
• jerry-D / HedgeHog-Fused-Spiking-Neural-Network-Emulator-Compute-Engine
  HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…
  ☆60Updated 8 months ago