WeitaoZhu / CMOS_VLSI_Design

Related projects: ⓘ

• MasterPu2020 / IC-design-general
  数字IC设计笔试相关的一些电路代码
  ☆10Updated 11 months ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆124Updated 2 years ago
• WeitaoZhu / Integrated_Circuits_and_Semiconductor
  Integrated_Circuits_and_Semiconductor 集成电路设计与半导体物理器件书籍
  ☆56Updated 2 years ago
• kaitoukito / Integrated-Circuit-Textbooks
  Collect some IC textbooks for learning.
  ☆96Updated 2 years ago
• wataru030-XIAOHEI / My-RISCV64-CORE-writing
  一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
  ☆24Updated 2 years ago
• dumpo / digital_IC_design_notes
  数字IC设计 学习笔记
  ☆110Updated 2 years ago
• CustomizableComputingLab / CustomizableComputingLab.github.io
  ☆133Updated last month
• peilin-chen / Zhulong-RISCV-CPU
  CPU Design Based on RISCV ISA
  ☆70Updated 3 months ago
• Daniel-GGB / My-Digital-IC-Library
  我的数字IC厂库：Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;
  ☆62Updated 2 years ago
• Yawei-Ding / ysyx_riscv64_cpu
  ☆50Updated last year
• OSCPU / ysyxSoC
  ☆75Updated last week
• tyxiumud / gvim_for_verilog
  this repository is vim cfg for verilog.
  ☆36Updated last month
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆95Updated 2 months ago
• loykylewong / FPGA-Application-Development-and-Simulation
  《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).
  ☆123Updated 3 months ago
• lauchinyuan / Booth4_wallace_MULT16_16
  A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction
  ☆27Updated last month
• ysyx-ta / ysyx-summer-readings
  ☆55Updated last month
• flyjancy / CortexM0_SoC_Task
  Step by step tutorial for building CortexM0 SoC
  ☆35Updated 2 years ago
• wuzeyou / Multiplier16X16
  Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder
  ☆99Updated 11 years ago
• liuqdev / 8-bits-RISC-CPU-Verilog
  Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。
  ☆131Updated 5 years ago
• gzzyyxh / Quafu
  A small SoC with a pipeline 32-bit RISC-V CPU.
  ☆60Updated 2 years ago
• OpenXiangShan / XS-Verilog-Library
  ☆35Updated 2 years ago
• xiaoan109 / ysyx-workbench
  ☆10Updated last year
• ChunxuGuo / SummerSchool2022
  ☆57Updated last year
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆36Updated 4 years ago
• JackHCC / Digital-Integrated-Circuit-Design
  北京大学数字集成电路设计课程作业—FPGA设计【Assignment of digital integrated circuit design course of Peking University】
  ☆19Updated 2 years ago
• suisuisi / FPGAandGames
  FPGA实现各种小游戏，学习并快乐着
  ☆57Updated 2 years ago
• Giftwen / CourseDigitalIC
  国科大高等数字集成电路分析与设计课程2022fall
  ☆22Updated last year
• xupsh / Digital-Design-Lab
  ☆201Updated 3 years ago
• qninth / awesome-digital-ic
  A collection of great digital IC project/tutorial/website etc..
  ☆85Updated 2 years ago
• OSCPU / ysyx-workbench
  ☆108Updated 3 weeks ago