Alternatives and similar repositories for CMOS_VLSI_Design

Users that are interested in CMOS_VLSI_Design are comparing it to the libraries listed below

• lauchinyuan / Booth4_wallace_MULT16_16
  A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction
  ☆57Updated last year
• kaitoukito / Integrated-Circuit-Textbooks
  Collect some IC textbooks for learning.
  ☆167Updated 3 years ago
• peilin-chen / Zhulong-RISCV-CPU
  CPU Design Based on RISCV ISA
  ☆122Updated last year
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆164Updated 3 years ago
• out-of-order55 / booth-multiplier
  基4booth乘法器设计与验证
  ☆13Updated last year
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆134Updated 5 months ago
• BIGWJZ / VLSI-DSP-Review
  ☆76Updated 5 years ago
• CustomizableComputingLab / CustomizableComputingLab.github.io
  ☆149Updated last month
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆104Updated 5 years ago
• dumpo / digital_IC_design_notes
  数字IC设计 学习笔记
  ☆155Updated 3 years ago
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆88Updated 3 years ago
• wuzeyou / Multiplier16X16
  Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder
  ☆120Updated 12 years ago
• dldldlfma / super_small_toy_tpu
  ☆42Updated 4 years ago
• YutingJiang / Digital_IC_Backend_Interview
  A collection of possible interview questions for ASIC PD position
  ☆23Updated 4 years ago
• MasterPu2020 / IC-design-general
  数字IC设计笔试相关的一些电路代码
  ☆13Updated 2 years ago
• Daniel-GGB / My-Digital-IC-Library
  我的数字IC厂库：Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;
  ☆99Updated 3 years ago
• wangjidwb123 / AHB-SRAMC
  IC Verification & SV Demo
  ☆54Updated 4 years ago
• Giftwen / CourseDigitalIC
  国科大高等数字集成电路分析与设计课程2022fall
  ☆29Updated 2 years ago
• 9334swjtu / PYNQ_softmax
  achieve softmax in PYNQ with heterogeneous computing.
  ☆66Updated 6 years ago
• RV-BOSC / OpenNoC
  ☆198Updated 3 months ago
• abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU
  IC implementation of Systolic Array for TPU
  ☆285Updated 11 months ago
• brentwang-lab / uvm_tb_gen
  This is for uvm_tb_gen
  ☆42Updated 8 months ago
• huangxc6 / E203_CNN_Genesys2
  Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.
  ☆22Updated last year
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆45Updated 5 years ago
• tyxiumud / gvim_for_verilog
  this repository is vim cfg for verilog.
  ☆50Updated last year
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆105Updated 5 years ago
• ytliu74 / RISCV_Verilog
  RISC-V SOC (both single and pipeline) implemented in Verilog. Passed all test codes provided by TA.
  ☆19Updated 2 years ago
• ForrestBlue / cortexm0ds
  ☆69Updated 9 years ago
• dumpo / my_verilog_projects
  数字IC秋招项目、手撕代码
  ☆38Updated last year
• devindang / openip-hdl
  Open IP in Hardware Description Language.
  ☆28Updated 2 years ago