WeitaoZhu / CMOS_VLSI_DesignLinks
COMS 超大规模集成电路设计书籍
☆24Updated 3 years ago
Alternatives and similar repositories for CMOS_VLSI_Design
Users that are interested in CMOS_VLSI_Design are comparing it to the libraries listed below
Sorting:
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆48Updated 10 months ago
- CPU Design Based on RISCV ISA☆113Updated last year
- Collect some IC textbooks for learning.☆146Updated 2 years ago
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆90Updated 3 years ago
- AXI协议规范中文翻译版☆152Updated 2 years ago
- Some useful documents of Synopsys☆75Updated 3 years ago
- AXI总线连接器☆99Updated 5 years ago
- upgrade to e203 (a risc-v core)☆44Updated 4 years ago
- 一生一芯 , ysyx , npc . the repo of the YSYX project . a riscv-64 CPU . writing .☆29Updated 2 years ago
- 国科大高等数字集成电路分析与设计课程2022fall☆25Updated 2 years ago
- ☆65Updated 9 years ago
- ☆86Updated last month
- ☆63Updated 4 years ago
- 数字IC设计 学习笔记☆138Updated 3 years ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆19Updated last year
- 基4booth乘法器设计与验证☆12Updated last year
- ☆163Updated last month
- ☆70Updated 4 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆118Updated last month
- Mirror of william_william/uvm-mcdf on Gitee☆23Updated 2 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆65Updated 10 months ago
- An AXI4 crossbar implementation in SystemVerilog☆157Updated last week
- Open IP in Hardware Description Language.☆24Updated last year
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆207Updated last year
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- SDRAM controller with AXI4 interface☆94Updated 5 years ago
- 北京大学数字集成电路设计课程作业—FPGA设计【Assignment of digital integrated circuit design course of Peking University】☆37Updated 3 years ago
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例,并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆25Updated 2 years ago
- a training-target implementation of rv32im, designed to be simple and easy to understand☆60Updated 3 years ago
- ☆146Updated this week