R2MDC FFT/IFFT processor adaptive to 64/128/256/512 point
☆18Dec 23, 2025Updated 3 months ago
Alternatives and similar repositories for multi-mode-fft-processor
Users that are interested in multi-mode-fft-processor are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- R22SDF FFT VLSI/FPGA investigate and implementation☆16Apr 22, 2022Updated 3 years ago
- 大三上做的本科毕设，包含BNN的替代梯度训练，verilog电路实现，完成180nm工艺流片。☆22Jun 30, 2025Updated 8 months ago
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆11Jan 8, 2022Updated 4 years ago
- ☆11Oct 24, 2024Updated last year
- 基于FPGA的FFT☆19Feb 18, 2019Updated 7 years ago
- Original test vector of RISC-V Vector Extension☆14Mar 23, 2021Updated 5 years ago
- Radix-4 1024 point fft in verilog☆13Apr 29, 2020Updated 5 years ago
- ☆27Aug 2, 2021Updated 4 years ago
- Hardware and software implementation of Sparsely-active SNNs☆22Mar 6, 2026Updated 2 weeks ago
- simple experiments to reproduce the CReLU paper☆12Jun 17, 2016Updated 9 years ago
- 基于Xilinx FPGA的通用型 CNN卷积神经网络加速器，本设计基于KV260板卡，MpSoC架构均可移植☆19Dec 13, 2024Updated last year
- MIPS 57条指令五级流水线cpu (verilog实现+详细注释)☆11Jan 11, 2022Updated 4 years ago
- Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022☆11Sep 21, 2022Updated 3 years ago
- ☆17Apr 7, 2022Updated 3 years ago
- Nuclei AI Library Optimized For RISC-V Vector☆14Oct 15, 2025Updated 5 months ago
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆26Mar 13, 2025Updated last year
- ☆10Sep 1, 2020Updated 5 years ago
- ☆31Aug 8, 2020Updated 5 years ago
- 💻 C++ 由简及繁，学习历程☆13Nov 1, 2021Updated 4 years ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆34Aug 13, 2024Updated last year
- Template for project1 TPU☆23May 1, 2021Updated 4 years ago
- Coarse Grained Reconfigurable Arrays with Chisel3☆12Jul 1, 2024Updated last year
- Fast Matrix Multiplication Implementation in C programming language. This matrix multiplication algorithm is similar to what Numpy uses t…☆41Jun 6, 2021Updated 4 years ago
- ☆12Jun 22, 2023Updated 2 years ago
- This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…☆11Aug 3, 2022Updated 3 years ago
- 2048 Game created via Verilog, loaded on an FPGA board and VGA monitor.☆13Mar 25, 2022Updated 3 years ago
- General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。☆91Mar 6, 2025Updated last year
- Project of an integrated UART: RTL, Verification, Physical Implementation (Innovus) and GDSII.☆16May 28, 2021Updated 4 years ago
- FPGA创新设计大赛全国二等奖，Multi-functional Game Console Based on RISC-V.(基于紫光FPGA的RSIC V多功能游戏机)☆11Aug 16, 2024Updated last year
- An AXI DDR3 SDRAM controller for FPGA☆45Dec 30, 2023Updated 2 years ago
- A simple camera board using GMAX3412 1" 4K@30fps global shutter sensor☆20Dec 21, 2025Updated 3 months ago
- Implements kernels with RISC-V Vector☆22Mar 24, 2023Updated 2 years ago
- ☆36Jun 19, 2023Updated 2 years ago
- ☆10Oct 8, 2021Updated 4 years ago
- 记录一下夏季学期计算机设计与实践课上写的RISC-V单周期CPU和RISC-V五级流水线CPU☆14Sep 7, 2021Updated 4 years ago
- This is a simple Risc-v core for software simulation on FPGA.☆10Apr 9, 2022Updated 3 years ago
- TMMA: A Tiled Matrix Multiplication Accelerator for Self-Attention Projections in Transformer Models, optimized for edge deployment on Xi…☆27Mar 24, 2025Updated 11 months ago
- ☆22May 15, 2021Updated 4 years ago
- [FPL'24] This repository contains the source code for the paper “Revealing Untapped DSP Optimization Potentials for FPGA-based Systolic M…☆21May 6, 2024Updated last year