BriMonzZY / multi-mode-fft-processorLinks
R2MDC FFT/IFFT processor adaptive to 64/128/256/512 point
☆16Updated last month
Alternatives and similar repositories for multi-mode-fft-processor
Users that are interested in multi-mode-fft-processor are comparing it to the libraries listed below
Sorting:
- ☆11Updated 5 years ago
- ☆58Updated 6 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆16Updated 3 years ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆21Updated 10 months ago
- commit rtl and build cosim env☆15Updated last year
- 自建 chisel 工程模板☆14Updated 2 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆44Updated 3 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆14Updated 3 years ago
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆24Updated 10 months ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆32Updated last year
- 第四届全国大学生嵌入式比赛SoC☆11Updated 3 years ago
- Tensor Processing Unit implementation in Verilog☆13Updated 10 months ago
- Open IP in Hardware Description Language.☆29Updated 2 years ago
- ☆31Updated 5 years ago
- 简单的未优化的SRT除法器☆12Updated last year
- ☆40Updated 6 years ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆46Updated 2 years ago
- ☆70Updated 3 years ago
- CNN accelerator using NoC architecture☆17Updated 7 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆53Updated 2 years ago
- YSYX RISC-V Project NJU Study Group☆16Updated last year
- 包括同步FIFO(输入输出位宽相同),异步FIFO(输入输出位宽相同),异步FIFO(能实现输出数据位宽是输入数据位宽的1/2或2倍)☆23Updated 3 years ago
- RTL code of some arbitration algorithm☆15Updated 6 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆55Updated 4 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- upgrade to e203 (a risc-v core)☆45Updated 5 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆67Updated 2 years ago
- Input / Output Physical Memory Protection Unit for RISC-V☆15Updated 2 years ago
- 大三上做的本科毕设,包含BNN的替代梯度训练,verilog电路实现,完成180nm工艺流片。☆21Updated 7 months ago
- ☆37Updated 7 years ago