BriMonzZY / multi-mode-fft-processorLinks
R2MDC FFT/IFFT processor adaptive to 64/128/256/512 point
☆14Updated last week
Alternatives and similar repositories for multi-mode-fft-processor
Users that are interested in multi-mode-fft-processor are comparing it to the libraries listed below
Sorting:
- ☆34Updated 6 years ago
- 自建 chisel 工程模板☆14Updated 2 years ago
- ☆10Updated 5 years ago
- commit rtl and build cosim env☆15Updated last year
- ☆18Updated 2 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆13Updated 2 years ago
- ☆29Updated 4 years ago
- ☆51Updated 6 years ago
- Open IP in Hardware Description Language.☆24Updated last year
- verification of simple axi-based cache☆18Updated 6 years ago
- RTL code of some arbitration algorithm☆14Updated 5 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆62Updated last year
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆20Updated 11 months ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆41Updated last year
- A small Neural Network Processor for Edge devices.☆11Updated 2 years ago
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆18Updated 4 months ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆21Updated 2 months ago
- Tensor Processing Unit implementation in Verilog☆9Updated 4 months ago
- ☆56Updated 2 years ago
- A MCU implementation based PODES-M0O☆18Updated 5 years ago
- upgrade to e203 (a risc-v core)☆44Updated 4 years ago
- HYF's high quality verilog codes☆14Updated 6 months ago
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆26Updated 8 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆10Updated last year
- xkDLA:XinKai Deep Learning Accelerator (RTL)☆34Updated last year
- 128KB AXI cache (32-bit in, 256-bit out)☆51Updated 4 years ago
- A Verilog implementation of a processor cache.☆28Updated 7 years ago