basemhesham / Design-and-ASIC-Implementation-of-UART
This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been implemented by using Verilog description language which has been synthesized using Design Compiler and Back End design using Synopsys IC Compiler II
☆15Updated 8 months ago
Alternatives and similar repositories for Design-and-ASIC-Implementation-of-UART:
Users that are interested in Design-and-ASIC-Implementation-of-UART are comparing it to the libraries listed below
- ☆16Updated 9 months ago
- ☆38Updated 3 years ago
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆17Updated 3 years ago
- Synchronous FIFO Testbench☆10Updated 2 years ago
- ☆16Updated 2 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆53Updated 2 years ago
- Architectural design of data router in verilog☆28Updated 5 years ago
- Two Level Cache Controller implementation in Verilog HDL☆39Updated 4 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆21Updated last year
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆20Updated 3 years ago
- ☆11Updated last week
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆28Updated 2 years ago
- UART design in SV and verification using UVM and SV☆39Updated 5 years ago
- AXI Interconnect☆47Updated 3 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆31Updated 2 years ago
- To develop Arm Cortex-M0 based SoCs, from creating high-level functional specifications to design, implementation and testing on FPGA pla…☆22Updated 4 years ago
- UVM Testbench to verify serial transmission of data between SPI master and slave☆38Updated 4 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆36Updated 2 years ago
- ☆26Updated 5 years ago
- Verification IP for I2C protocol☆40Updated 3 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆22Updated 2 years ago
- Master and Slave made using AMBA AXI4 Lite protocol.☆26Updated 4 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆56Updated last year
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆19Updated 10 months ago
- ☆16Updated last year
- Verification IP for APB protocol☆56Updated 4 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆42Updated 9 months ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆80Updated last year
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆47Updated 4 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆19Updated 12 years ago