This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been implemented by using Verilog description language which has been synthesized using Design Compiler and Back End design using Synopsys IC Compiler II
☆29Apr 29, 2024Updated 2 years ago
Alternatives and similar repositories for Design-and-ASIC-Implementation-of-UART
Users that are interested in Design-and-ASIC-Implementation-of-UART are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- DTMF Receiver: Logic Synthesis and Physical Design using genus and innovus in 90nm process node☆15Dec 1, 2023Updated 2 years ago
- Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo☆14Jul 31, 2024Updated last year
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.☆28Feb 11, 2024Updated 2 years ago
- Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.☆27Sep 8, 2024Updated last year
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆13Aug 25, 2021Updated 4 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- General Purpose IO with APB4 interface☆16May 10, 2024Updated 2 years ago
- ☆17Sep 16, 2022Updated 3 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- ☆22Sep 26, 2025Updated 7 months ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 4 years ago
- RTL to GDS via Cadence Tools☆17May 17, 2022Updated 3 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆19May 29, 2018Updated 7 years ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆20Aug 19, 2024Updated last year
- ☆18Apr 5, 2015Updated 11 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆113Feb 22, 2024Updated 2 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆53Jan 4, 2022Updated 4 years ago
- Examples of the TCL Scripts for different purposes and for VLSI Physical Design are provided here for your reference☆35Dec 30, 2022Updated 3 years ago
- A SPI Master IP written in verilog which is then used to output characters entered on a keypad to a serial LCD screen☆20Dec 5, 2014Updated 11 years ago
- This repo is for Edge Vision SoC framework, which facilitates quick porting of users' design for Edge AI and Vision solutions.☆28Feb 13, 2026Updated 2 months ago
- Compressed Sensing signal decoding with DNN oracle on STM32☆16Apr 5, 2021Updated 5 years ago
- This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…☆47Mar 3, 2024Updated 2 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆85Oct 11, 2019Updated 6 years ago
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆16May 23, 2024Updated last year
- Plugin manager using Qt framework to create Qt application based on custom loadable plugins☆13Oct 12, 2023Updated 2 years ago
- iEDA water-drop training initiative☆14Sep 10, 2024Updated last year
- AVR CPU Core Implementation in Verilog HDL.☆15Oct 28, 2018Updated 7 years ago
- 64-bit MISC Architecture CPU☆13Dec 13, 2016Updated 9 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆81Nov 26, 2020Updated 5 years ago
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆15Oct 16, 2021Updated 4 years ago
- This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.☆12Sep 6, 2023Updated 2 years ago
- Personal mirror for adv_debug_sys☆11Aug 23, 2011Updated 14 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆78Dec 7, 2020Updated 5 years ago
- Small and simple, primitive SoC with GPU, CPU, RAM, GPIO☆14Dec 29, 2016Updated 9 years ago
- Verilog IP Cores & Tests☆13May 3, 2018Updated 8 years ago
- ☆12Nov 13, 2022Updated 3 years ago
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- Verilog CAN controller that is compatible to the SJA 1000.☆16Apr 17, 2021Updated 5 years ago
- Build infrastructure for class-wide tapeout for 18-224/624 Intro to Open Source Chip Design, Spring 2023☆21Aug 10, 2023Updated 2 years ago