GramThanos / CPU-on-Vivado-HLS
A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS
☆18Updated 5 years ago
Related projects ⓘ
Alternatives and complementary repositories for CPU-on-Vivado-HLS
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆65Updated 3 years ago
- ☆23Updated 3 years ago
- Domain-Specific Architecture Generator 2☆20Updated 2 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆46Updated 7 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆59Updated 11 months ago
- ☆19Updated last year
- cycle accurate Network-on-Chip Simulator☆25Updated last year
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆44Updated 2 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆47Updated 2 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆39Updated 4 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆29Updated 2 years ago
- ☆22Updated 5 years ago
- ☆21Updated last month
- A Scalable BFS Accelerator on FPGA-HBM Platform☆13Updated 9 months ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆23Updated last month
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- NPUsim: Full-system, Cycle-accurate, Value-aware NPU Simulator☆24Updated last week
- A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency…☆18Updated 3 years ago
- CGRA framework with vectorization support.☆19Updated this week
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆47Updated 4 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆80Updated last month
- Tests for example Rocket Custom Coprocessors☆69Updated 4 years ago
- The gem5-X open source framework (based on the gem5 simulator)☆38Updated last year
- ☆15Updated 3 years ago
- The RTL source for AnyCore RISC-V☆30Updated 2 years ago
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆12Updated 4 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆63Updated 5 years ago
- HLS for Networks-on-Chip☆31Updated 3 years ago
- NeuroSpector: Dataflow and Mapping Optimization of Deep Neural Network Accelerators☆17Updated last week