GramThanos / CPU-on-Vivado-HLSLinks
A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS
☆18Updated 5 years ago
Alternatives and similar repositories for CPU-on-Vivado-HLS
Users that are interested in CPU-on-Vivado-HLS are comparing it to the libraries listed below
Sorting:
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆69Updated last year
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆50Updated 8 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆79Updated 3 years ago
- ☆31Updated 3 months ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆75Updated 6 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- ☆92Updated last year
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- ☆36Updated 4 years ago
- cycle accurate Network-on-Chip Simulator☆28Updated 2 years ago
- ☆60Updated 2 months ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆28Updated 3 weeks ago
- A DSL for Systolic Arrays☆80Updated 6 years ago
- ☆24Updated 4 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 3 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆42Updated 7 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 3 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆58Updated 3 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆93Updated 9 months ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆36Updated 6 months ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Updated 5 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆80Updated 11 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆73Updated this week
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆59Updated 2 weeks ago