Alternatives and similar repositories for VerilogCodingStyle

Users that are interested in VerilogCodingStyle are comparing it to the libraries listed below

• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆139Updated last year
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆104Updated last year
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆139Updated last year
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆80Updated 3 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆214Updated 2 years ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆160Updated 3 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆170Updated this week
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆106Updated 4 years ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆90Updated last year
• Practical-UVM-Step-By-Step / Practical-UVM-Step-By-Step
  This is the main repository for all the examples for the book Practical UVM
  ☆201Updated 4 years ago
• hellovimo / uvm_testbench_gen
  Novel GUI Based UVM Testbench Template Builder
  ☆141Updated 4 years ago
• RV-BOSC / OpenNoC
  ☆184Updated 2 months ago
• emwzq / example_uvm
  UVM实战随书源码
  ☆54Updated 6 years ago
• ForrestBlue / cortexm0ds
  ☆68Updated 9 years ago
• OpenXiangShan / XS-Verilog-Library
  ☆42Updated 3 years ago
• microdynamics-cpu / tree-core-ide
  The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…
  ☆107Updated 2 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆121Updated 11 years ago
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆141Updated 6 months ago
• ic7x24 / verilog-mini-demo
  Verilog极简教程
  ☆37Updated 6 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆70Updated 4 years ago
• ljgibbslf / SM3_core
  ☆143Updated 4 years ago
• zhajio1988 / YASA
  Yet Another Simulation Architecture
  ☆73Updated 4 years ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆188Updated 3 years ago
• andres-mancera / ethernet_10ge_mac_SV_UVM_tb
  SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
  ☆147Updated 7 years ago
• bytedance / ic_flow_platform
  IFP (ic flow platform) is an integrated circuit design flow platform, mainly used for IC process specification management and data flow …
  ☆183Updated 2 months ago
• zhajio1988 / Open_RegModel
  Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
  ☆69Updated 5 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆103Updated 5 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆79Updated 7 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆94Updated 4 years ago
• airin711 / Verilog-caches
  Various caches written in Verilog-HDL
  ☆125Updated 10 years ago