Lingrui98/RISC-V-book external links

---

GitHub - View repository

GitHub.dev - Open in online code editor

Star history - Growth chart over time

deps.dev - Dependencies and security vulnerabilities

Gitingest - Export source code for LLM usage

Repomix - Export source code for LLM usage

uithub - Export source code for LLM usage

Close

Lingrui98/RISC-V-book

Readme badge preview -

If you own this repo, copy the snippet below and add it to your README.md

---

Copy

[![RelatedRepos](https://img.shields.io/badge/related-repos-yellow)](https://relatedrepos.com/gh/Lingrui98/RISC-V-book)

Close

Lingrui98 / RISC-V-bookView on GitHubMore

• External links
• Readme badge

A translation project of the RISC-V reader

☆173Jan 2, 2024Updated 2 years ago

Alternatives and similar repositories for RISC-V-book

Users that are interested in RISC-V-book are comparing it to the libraries listed below

• ljwljwljwljw / DiplomaticBackend

  View on GitHub
  ☆17Mar 17, 2022Updated 3 years ago
• comparch-security / FlexiCAS

  View on GitHub
  A Flexible Cache Architectural Simulator
  ☆17Sep 16, 2025Updated 5 months ago
• zlagpacan / LOROF

  View on GitHub
  Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU
  ☆15Feb 23, 2026Updated last week
• whutddk / Rift2Core

  View on GitHub
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆39Feb 6, 2024Updated 2 years ago
• pulp-platform / ri5cy_gnu_toolchain

  View on GitHub
  ☆23Mar 15, 2025Updated 11 months ago
• Lichee-Pi / Tang_Doc_Backup

  View on GitHub
  Lichee Tang - A circuit board of RISC-V architecture http://tang.lichee.pro
  ☆18Jul 19, 2019Updated 6 years ago
• nucleisys / n200-doc

  View on GitHub
  Deprecated, no longer updated, please change to https://www.nucleisys.com/index.php
  ☆25Mar 24, 2021Updated 4 years ago
• emb-riscv / specs-markdown

  View on GitHub
  The preliminary 'RISC-V microcontroller profile' specs; for convenience, use markdown.
  ☆28Feb 15, 2022Updated 4 years ago
• baochuquan / RISCV-MMU

  View on GitHub
  ☆14Nov 5, 2017Updated 8 years ago
• xfguo / riscv-openwrt-port

  View on GitHub
  RISC-V OpenWrt Port
  ☆17Oct 30, 2018Updated 7 years ago
• lingscale / cc01

  View on GitHub
  ☆30Mar 13, 2025Updated 11 months ago
• cnrv / riscv-soc-book

  View on GitHub
  关于RISC-V你所需要知道的一切
  ☆560Apr 1, 2023Updated 2 years ago
• open-isa-cn / vega-lite

  View on GitHub
  Software, tools, and documentation for RV32-VEGA-Lite platform
  ☆65Apr 27, 2019Updated 6 years ago
• shinezyy / micro-arch-training

  View on GitHub
  How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design
  ☆626Aug 13, 2024Updated last year
• riscv-non-isa / riscv-sbi-doc

  View on GitHub
  Documentation for the RISC-V Supervisor Binary Interface
  ☆455Feb 6, 2026Updated last month
• pulp-platform / axi_node

  View on GitHub
  AXI X-Bar
  ☆19Apr 8, 2020Updated 5 years ago
• cnrv / home

  View on GitHub
  为推广RISC-V尽些薄力
  ☆312Jun 22, 2023Updated 2 years ago
• IBM / rocc-software

  View on GitHub
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆53Jul 14, 2020Updated 5 years ago
• OpenXiangShan / CoupledL2

  View on GitHub
  Open-source non-blocking L2 cache
  ☆54Updated this week
• RoaLogic / adv_dbg_if

  View on GitHub
  Universal Advanced JTAG Debug Interface
  ☆17May 10, 2024Updated last year
• lizhirui / DreamCoreV2

  View on GitHub
  ☆22Apr 16, 2023Updated 2 years ago
• riscv-non-isa / riscv-elf-psabi-doc

  View on GitHub
  A RISC-V ELF psABI Document
  ☆832Feb 6, 2026Updated last month
• ved-rivos / iommu-rtl

  View on GitHub
  RISC-V IOMMU in verilog
  ☆23Jun 18, 2022Updated 3 years ago
• nvdla / tlm2c

  View on GitHub
  Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…
  ☆19Aug 13, 2018Updated 7 years ago
• embecosm / riscv-gdbserver

  View on GitHub
  GDB Server for interacting with RISC-V models, boards and FPGAs
  ☆20Sep 16, 2019Updated 6 years ago
• LvNA-system / labeled-RISC-V

  View on GitHub
  ☆169Jul 16, 2021Updated 4 years ago
• NJU-ProjectN / nemu

  View on GitHub
  NJU EMUlator, a full system x86/mips32/riscv32/riscv64 emulator for teaching
  ☆1,091Nov 14, 2025Updated 3 months ago
• riscv-software-src / riscv-isa-sim

  View on GitHub
  Spike, a RISC-V ISA Simulator
  ☆3,024Feb 26, 2026Updated last week
• Minres / SystemC-Components

  View on GitHub
  A SystemC productivity library: https://minres.github.io/SystemC-Components/
  ☆131Feb 25, 2026Updated last week
• riscv-boom / riscv-boom

  View on GitHub
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆2,083Feb 5, 2026Updated last month
• metro94 / RV-DAP-Plus

  View on GitHub
  ☆25Sep 12, 2021Updated 4 years ago
• Openwide-Ingenierie / CHIP-8-UEFI

  View on GitHub
  CHIP-8 emulator for UEFI
  ☆12Jun 12, 2017Updated 8 years ago
• lishuhuakai / Regular-Expression

  View on GitHub
  一个简易的正则表达式引擎!
  ☆10Apr 9, 2017Updated 8 years ago
• cnrv / RVWC2021-slides

  View on GitHub
  第一届 RISC-V 中国峰会的幻灯片等资料存放
  ☆38Nov 17, 2022Updated 3 years ago
• OpenXiangShan / XiangShan

  View on GitHub
  Open-source high-performance RISC-V processor
  ☆6,885Updated this week
• pulp-platform / gvsoc

  View on GitHub
  Pulp virtual platform
  ☆24Jul 16, 2025Updated 7 months ago
• riscv / riscv-isa-manual

  View on GitHub
  RISC-V Instruction Set Manual
  ☆4,514Updated this week
• riscv-non-isa / riscv-asm-manual

  View on GitHub
  RISC-V Assembly Programmer's Manual
  ☆1,615Feb 26, 2026Updated last week
• jinhang1997 / Q-A-for-PA-2018

  View on GitHub
  PA2018常见问题解答（持续更新，更新频率1-2天/次），欢迎star
  ☆31Jun 24, 2018Updated 7 years ago