c-sky / xuantie-vector-demosLinks
☆10Updated 4 years ago
Alternatives and similar repositories for xuantie-vector-demos
Users that are interested in xuantie-vector-demos are comparing it to the libraries listed below
Sorting:
- GNU toolchain for Xuantie RISC-V CPU, including GCC and Binutils ……☆99Updated last month
- ☆42Updated 3 years ago
- PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases☆22Updated 4 years ago
- ☆11Updated 4 years ago
- TVM for chips base on Xuantie CPU, an open deep learning compiler stack.☆30Updated 11 months ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆68Updated 10 months ago
- 平头哥玄铁C910的LLVM工具链支持,由PLCT实验室提供,非官方版本☆70Updated 4 years ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆101Updated 2 years ago
- Basic floating-point components for RISC-V processors☆65Updated 5 years ago
- ☆86Updated 3 years ago
- Following the RISC-V IME extension standard, and reusing Vector register resources, these instructions can bring more than a tenfold perf…☆61Updated 9 months ago
- This is a repo for recording and reporting RISCV platform's test and measurement continuously.☆59Updated last year
- ☆89Updated 2 months ago
- RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…☆15Updated last year
- A translator from ARM NEON intrinsics to RISCV-V Extension implementation☆32Updated 9 months ago
- RISC-V Summit China 2023☆40Updated last year
- ☆31Updated 2 months ago
- Linux kernel source tree☆43Updated 3 months ago
- Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.☆27Updated 3 years ago
- a clone of POCL that includes RISC-V newlib devices support and Vortex☆42Updated 2 months ago
- An optimized neural network operator library for chips base on Xuantie CPU.☆89Updated 11 months ago
- Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension☆43Updated 4 years ago
- ☆35Updated 10 months ago
- Chisel RISC-V Vector 1.0 Implementation☆98Updated 3 weeks ago
- RISC-V Matrix Specification☆22Updated 6 months ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆42Updated 2 years ago
- A bare-metal application to test specific features of the risc-v hypervisor extension☆40Updated last year
- PCI Express controller model☆57Updated 2 years ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆40Updated last year
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆55Updated last year