c-sky / xuantie-vector-demosLinks
☆10Updated 4 years ago
Alternatives and similar repositories for xuantie-vector-demos
Users that are interested in xuantie-vector-demos are comparing it to the libraries listed below
Sorting:
- GNU toolchain for Xuantie RISC-V CPU, including GCC and Binutils ……☆99Updated 2 months ago
- ☆42Updated 3 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆68Updated 11 months ago
- A translator from ARM NEON intrinsics to RISCV-V Extension implementation☆34Updated 9 months ago
- An optimized neural network operator library for chips base on Xuantie CPU.☆89Updated 11 months ago
- ☆11Updated 4 years ago
- ☆35Updated 11 months ago
- RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…☆16Updated last year
- TVM for chips base on Xuantie CPU, an open deep learning compiler stack.☆30Updated 11 months ago
- 平头哥玄铁C910的LLVM工具链支持,由PLCT实验室提供,非官方版本☆70Updated 4 years ago
- PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases☆22Updated 4 years ago
- Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension☆43Updated 4 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆42Updated 2 years ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆102Updated 2 years ago
- Basic floating-point components for RISC-V processors☆65Updated 5 years ago
- Translate RISC-V Vector Assembly from v1.0 to v0.7☆34Updated 10 months ago
- ☆86Updated 3 years ago
- This is a repo for recording and reporting RISCV platform's test and measurement continuously.☆59Updated last year
- RISC-V Summit China 2023☆40Updated last year
- A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS☆23Updated 3 weeks ago
- ☆17Updated 2 years ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆40Updated last year
- a clone of POCL that includes RISC-V newlib devices support and Vortex☆42Updated 3 months ago
- Unit tests generator for RVV 1.0☆88Updated last month
- xkDLA:XinKai Deep Learning Accelerator (RTL)☆34Updated last year
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆98Updated 3 years ago
- Following the RISC-V IME extension standard, and reusing Vector register resources, these instructions can bring more than a tenfold perf…☆63Updated 10 months ago
- ☆62Updated 4 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- The multi-core cluster of a PULP system.☆101Updated this week