c-sky / xuantie-vector-demosLinks
☆10Updated 5 years ago
Alternatives and similar repositories for xuantie-vector-demos
Users that are interested in xuantie-vector-demos are comparing it to the libraries listed below
Sorting:
- GNU toolchain for Xuantie RISC-V CPU, including GCC and Binutils ……☆101Updated 5 months ago
- ☆90Updated 3 weeks ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆70Updated last year
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆108Updated 2 years ago
- Following the RISC-V IME extension standard, and reusing Vector register resources, these instructions can bring more than a tenfold perf…☆66Updated last year
- Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension☆43Updated 4 years ago
- ☆42Updated 3 years ago
- TVM for chips base on Xuantie CPU, an open deep learning compiler stack.☆30Updated last year
- 平头哥玄铁C910的LLVM工具链支持,由PLCT实验室提供,非官方版本☆74Updated 4 years ago
- ☆37Updated last year
- ☆11Updated 4 years ago
- A translator from ARM NEON intrinsics to RISCV-V Extension implementation☆38Updated 3 weeks ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆40Updated last year
- PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases☆22Updated 4 years ago
- RISC-V Summit China 2023☆40Updated last year
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆43Updated 2 years ago
- Chisel RISC-V Vector 1.0 Implementation☆111Updated 2 weeks ago
- Unit tests generator for RVV 1.0☆90Updated 2 weeks ago
- RiVEC Bencmark Suite☆121Updated 9 months ago
- RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…☆16Updated last year
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆41Updated last year
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆57Updated last year
- ☆17Updated 3 years ago
- An optimized neural network operator library for chips base on Xuantie CPU.☆93Updated last year
- RV64GC Linux Capable RISC-V Core☆33Updated last month
- muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.☆86Updated 3 weeks ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆62Updated 3 years ago
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆127Updated this week
- RISC-V Matrix Specification☆22Updated 9 months ago
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆36Updated 3 months ago