c-sky / xuantie-vector-demosLinks
☆10Updated 5 years ago
Alternatives and similar repositories for xuantie-vector-demos
Users that are interested in xuantie-vector-demos are comparing it to the libraries listed below
Sorting:
- GNU toolchain for Xuantie RISC-V CPU, including GCC and Binutils ……☆106Updated 8 months ago
- ☆89Updated 4 months ago
- PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases☆21Updated 5 years ago
- RISC-V Summit China 2023☆40Updated 2 years ago
- A translator from ARM NEON intrinsics to RISCV-V Extension implementation☆41Updated 4 months ago
- RV64GC Linux Capable RISC-V Core☆48Updated 2 months ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Updated last year
- RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…☆16Updated last year
- Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension☆43Updated 5 years ago
- 平头哥玄铁C910的LLVM工具链支持,由PLCT实验室提供,非官方版本☆76Updated 4 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆72Updated last year
- ☆11Updated 4 years ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆44Updated 2 years ago
- ☆38Updated last year
- RISC-V Packed SIMD Extension☆154Updated last month
- Chisel Cheatsheet☆34Updated 2 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Updated 3 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- Basic floating-point components for RISC-V processors☆67Updated 6 years ago
- ☆42Updated 3 years ago
- ☆18Updated 3 years ago
- TVM for chips base on Xuantie CPU, an open deep learning compiler stack.☆30Updated last year
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- An optimized neural network operator library for chips base on Xuantie CPU.☆96Updated last year
- PCI Express controller model☆71Updated 3 years ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆27Updated 2 weeks ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆114Updated 2 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.☆27Updated 4 years ago
- Nuclei AI Library Optimized For RISC-V Vector☆14Updated 2 months ago