Alternatives and similar repositories for xuantie-vector-demos

Users that are interested in xuantie-vector-demos are comparing it to the libraries listed below

• XUANTIE-RV / xuantie-gnu-toolchain
  GNU toolchain for Xuantie RISC-V CPU, including GCC and Binutils ……
  ☆100Updated 3 months ago
• hushenwei2000 / rvv-atg
  RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…
  ☆16Updated last year
• riscvarchive / riscv-aclint
  ☆42Updated 3 years ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆69Updated last year
• XUANTIE-RV / tvm
  TVM for chips base on Xuantie CPU, an open deep learning compiler stack.
  ☆30Updated last year
• plctlab / rvv-benchmark
  PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases
  ☆22Updated 4 years ago
• cnrv / RVSC2023
  RISC-V Summit China 2023
  ☆40Updated last year
• compiler-dev / llvm-rv
  Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension
  ☆43Updated 4 years ago
• XUANTIE-RV / csi-nn2
  An optimized neural network operator library for chips base on Xuantie CPU.
  ☆90Updated last year
• riscv / riscv-CMOs
  ☆86Updated 3 years ago
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆41Updated last year
• space-mit / riscv-ime-extension-spec
  Following the RISC-V IME extension standard, and reusing Vector register resources, these instructions can bring more than a tenfold perf…
  ☆65Updated 11 months ago
• ISRC-CAS / c910-llvm
  平头哥玄铁C910的LLVM工具链支持，由PLCT实验室提供，非官方版本
  ☆72Updated 4 years ago
• riscv / riscv-bfloat16
  ☆35Updated last year
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆103Updated 2 months ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆88Updated 2 months ago
• Jerc007 / Open-GPGPU-FlexGrip-
  FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation
  ☆106Updated 2 years ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆66Updated 5 years ago
• riscvarchive / riscv-eabi-spec
  Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.
  ☆27Updated 4 years ago
• tum-ei-eda / muriscv-nn
  muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.
  ☆82Updated last month
• xjtuiair-cag / SiYuan
  A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS
  ☆24Updated last week
• rdolbeau / VexRiscvBPluginGenerator
  ☆17Updated 2 years ago
• openasic-org / xkDLA
  xkDLA：XinKai Deep Learning Accelerator (RTL)
  ☆34Updated last year
• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆40Updated last year
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆53Updated 5 years ago
• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆42Updated 5 months ago
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆42Updated 2 years ago
• msyksphinz-self / riscv-vector-tests
  Original test vector of RISC-V Vector Extension
  ☆13Updated 4 years ago
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆117Updated 7 months ago
• ved-rivos / iommu-rtl
  RISC-V IOMMU in verilog
  ☆17Updated 3 years ago