Alternatives and similar repositories for kamikaze

Users that are interested in kamikaze are comparing it to the libraries listed below

• Lichee-Pi / Tang_E203_Mini
  LicheeTang 蜂鸟E203 Core
  ☆198Updated 6 years ago
• SI-RISCV / hbird-e-sdk
  Deprecated, please go to https://github.com/riscv-mcu/hbird-sdk/
  ☆112Updated 4 years ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆127Updated 6 years ago
• ilg-archived / riscv-none-gcc
  The GNU MCU Eclipse RISC-V Embedded GCC
  ☆78Updated 6 years ago
• XUANTIE-RV / opene902
  OpenXuantie - OpenE902 Core
  ☆159Updated last year
• freecores / 8051
  8051 core
  ☆108Updated 11 years ago
• XUANTIE-RV / opene906
  OpenXuantie - OpenE906 Core
  ☆142Updated last year
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆84Updated 6 years ago
• CoreyChen922 / sata3_host_controller
  It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.
  ☆75Updated last year
• NXP / i3c-slave-design
  MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
  ☆130Updated 5 years ago
• riscv-mcu / hbird-sdk
  OpenSource HummingBird RISC-V Software Development Kit
  ☆165Updated last year
• maswx / vu13p
  国产VU13P加速卡资料
  ☆79Updated 7 months ago
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆70Updated 8 years ago
• openrisc / or1200
  OpenRISC 1200 implementation
  ☆172Updated 9 years ago
• risclite / R8051
  8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.
  ☆193Updated 6 years ago
• lizhirui / AXI-SDCard-High-Speed-Controller
  A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)
  ☆124Updated 3 years ago
• ljgibbslf / SM3_core
  ☆144Updated 5 years ago
• cjhonlyone / picorv32_Xilinx
  A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz
  ☆75Updated 4 years ago
• illustris / FreeRTOS-RISCV
  A port of FreeRTOS for the RISC-V ISA
  ☆77Updated 6 years ago
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆141Updated last year
• mczerski / SD-card-controller
  WISHBONE SD Card Controller IP Core
  ☆128Updated 3 years ago
• LiHao217 / RISC-V_article_paper_src
  riscv资料、论文等
  ☆144Updated 7 years ago
• freecores / turbo8051
  turbo 8051
  ☆29Updated 8 years ago
• PulseRain / Rattlesnake
  PulseRain Rattlesnake - RISCV RV32IMC Soft CPU
  ☆34Updated 5 years ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆275Updated 5 years ago
• siorpaes / BareBonesCortexM0
  Extremely basic CortexM0 SoC based on ARM DesignStart Eval
  ☆27Updated 7 years ago
• risclite / ARM9-compatible-soft-CPU-core
  This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…
  ☆89Updated 5 years ago
• flyjancy / CortexM0_SoC
  Cortex M0 based SoC
  ☆75Updated 4 years ago
• microdynamics-cpu / tree-core-ide
  The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…
  ☆112Updated 3 years ago
• sunyata000 / PODES-M0O
  A VerilogHDL MCU Core based ARMv6 Cortex-M0
  ☆21Updated 5 years ago