tmeissner / gatemate_experiments
Experiments with Cologne Chip's GateMate FPGA architecture
☆16Updated 10 months ago
Related projects: ⓘ
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆18Updated 6 months ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆19Updated 10 months ago
- Picorv32 SoC that uses only BRAM, not flash memory☆12Updated 5 years ago
- Quickly update a bitstream with new RAM contents☆14Updated 3 years ago
- RISCV CPU implementation tutorial steps for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga☆11Updated 10 months ago
- Drop In USB CDC ACM core for iCE40 FPGA☆33Updated 3 years ago
- Adapter to use Colorlight i5/i9 FPGA boards in a QMTech board form factor☆17Updated 2 years ago
- A configurable USB 2.0 device core☆30Updated 4 years ago
- PLEASE MOVE TO PAWSv2☆17Updated 2 years ago
- VHDL Code for infrastructural blocks (designed for FPGA)☆12Updated last year
- CologneChip GateMate FPGA Module: GMM-7550☆18Updated 7 months ago
- USB virtual model in C++ for Verilog☆26Updated 2 weeks ago
- crap-o-scope scope implementation for icestick☆20Updated 6 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆12Updated last year
- Use ECP5 JTAG port to interact with user design☆24Updated 3 years ago
- Reusable Verilog 2005 components for FPGA designs☆34Updated last year
- There are many RISC V projects on iCE40. This one is mine.☆13Updated 4 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆19Updated 2 years ago
- Simplified environment for litex☆13Updated 3 years ago
- Mini CPU design with JTAG UART support☆18Updated 3 years ago
- Standard HyperRAM core for ECP5 written in Litex/Migen☆14Updated 4 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆47Updated 2 weeks ago
- Examples and design pattern for VHDL verification☆15Updated 8 years ago
- RISC-V Processor written in Amaranth HDL☆31Updated 2 years ago
- This repository contains a makefile to easily install Symbiflow for the Xilinx 7 Series boards.☆10Updated 3 years ago
- This is a collection of the built in libraries of the VHDPlus IDE toghether with examples. Commits will be featured in the IDE with futur…☆18Updated 6 months ago
- Set up your GitHub Actions workflow with a OSS CAD Suite☆14Updated 5 months ago
- ULPI Link Wrapper (USB Phy Interface)☆21Updated 4 years ago
- CRUVI Standard Specifications☆17Updated 4 months ago
- Experimental FPGA project for streaming two MIPI CSI camera streams to an HDMI monitor using a ULX3S FPGA board☆26Updated last year