Alternatives and similar repositories for llhd

Users that are interested in llhd are comparing it to the libraries listed below

• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆18Updated 9 months ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆38Updated 4 years ago
• SRI-CSL / l3riscv
  An executable specification of the RISCV ISA in L3.
  ☆42Updated 6 years ago
• vegaluisjose / vast
  Verilog AST
  ☆21Updated 2 years ago
• rdaly525 / coreir
  ☆104Updated 3 years ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆35Updated 5 years ago
• ymanerka / rtlcheck
  RTLCheck
  ☆25Updated 7 years ago
• rems-project / sail-arm
  Sail version of Arm ISA definition, currently for Armv9.3-A, and with the previous Sail Armv8.5-A model
  ☆92Updated last month
• Coloquinte / quaigh
  Logic circuit analysis and optimization
  ☆45Updated last week
• lsils / kitty
  C++ truth table library
  ☆64Updated 6 months ago
• sabbaghm / c-ll-verilog
  An LLVM based mini-C to Verilog High-level Synthesis tool
  ☆39Updated 11 months ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆74Updated 5 years ago
• daniellustig / coatcheck
  COATCheck
  ☆13Updated 7 years ago
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆119Updated 8 months ago
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆49Updated 7 months ago
• Kuree / fsim
  Fiber-based SystemVerilog Simulator.
  ☆25Updated 3 years ago
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆55Updated last month
• Kuree / kratos
  Debuggable hardware generator
  ☆71Updated 2 years ago
• foshardware / lsc
  Libre Silicon Compiler
  ☆22Updated 4 years ago
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆66Updated 7 months ago
• cliffordwolf / bextdep
  Reference Hardware Implementations of Bit Extract/Deposit Instructions
  ☆24Updated 8 years ago
• mikeurbach / egg-netlist-synthesizer
  Using e-graphs to synthesize netlists from boolean logic.
  ☆14Updated 2 years ago
• cucapra / latte21
  Languages, Tools, and Techniques for Accelerator Design
  ☆33Updated 4 years ago
• SiliconSemantics / firrtlator
  firrtlator is a FIRRTL C++ library
  ☆23Updated 9 years ago
• SymbioticEDA / nerv
  Naive Educational RISC-V -- A simple single-stage RV32I processor
  ☆27Updated 5 years ago
• gokhankici / iodine
  Iodine: Verifying Constant-Time Execution of Hardware
  ☆15Updated 4 years ago
• cdonovick / peak
  Peak : Processor Specification Language ala Newell and Bell's ISP
  ☆20Updated 2 years ago
• daniellustig / pipecheck
  ☆19Updated 11 years ago
• CTSRD-CHERI / beri
  The BERI and CHERI processor and hardware platform
  ☆50Updated 8 years ago
• franzflasch / leiwand_rv32
  RISC-V RV32I CPU written in verilog
  ☆10Updated 5 years ago