maerhart / llhdLinks
A low-level intermediate representation for hardware description languages
☆28Updated 5 years ago
Alternatives and similar repositories for llhd
Users that are interested in llhd are comparing it to the libraries listed below
Sorting:
- An LLVM based mini-C to Verilog High-level Synthesis tool☆37Updated 6 months ago
- Verilog AST☆21Updated last year
- Logic circuit analysis and optimization☆43Updated 2 weeks ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- Sail version of Arm ISA definition, currently for Armv9.3-A, and with the previous Sail Armv8.5-A model☆87Updated 2 months ago
- Testing processors with Random Instruction Generation☆46Updated 2 weeks ago
- CoreIR Symbolic Analyzer☆74Updated 4 years ago
- The PE for the second generation CGRA (garnet).☆17Updated 4 months ago
- C++ truth table library☆59Updated last month
- RTLCheck☆22Updated 6 years ago
- Naive Educational RISC-V -- A simple single-stage RV32I processor☆27Updated 4 years ago
- ☆103Updated 3 years ago
- firrtlator is a FIRRTL C++ library☆23Updated 8 years ago
- An executable specification of the RISCV ISA in L3.☆42Updated 6 years ago
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 3 years ago
- Fiber-based SystemVerilog Simulator.☆25Updated 3 years ago
- BTOR2 MLIR project☆26Updated last year
- HeteroSim is a full system simulator supporting x86 multicore processors combined with a FPGA via bus-based architecture. Flexible design…☆21Updated 9 years ago
- A Hardware Pipeline Description Language☆45Updated 2 months ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆37Updated 4 years ago
- Iodine: Verifying Constant-Time Execution of Hardware☆13Updated 4 years ago
- CHERI-RISC-V model written in Sail☆64Updated 2 months ago
- The BERI and CHERI processor and hardware platform☆50Updated 8 years ago
- COATCheck☆13Updated 6 years ago
- Debuggable hardware generator☆69Updated 2 years ago
- A fast RISC-V emulator based on the RISC-V Sail model, and an experimental ARM one☆79Updated this week
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆32Updated last week
- Fast PnR toolchain for CGRA☆18Updated last year
- A enumerator for MLIR, relying on the information given by IRDL.☆19Updated 2 weeks ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆145Updated 3 weeks ago