Alternatives and similar repositories for llhd:

Users that are interested in llhd are comparing it to the libraries listed below

• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆34Updated 4 years ago
• sabbaghm / c-ll-verilog
  An LLVM based mini-C to Verilog High-level Synthesis tool
  ☆35Updated last year
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆17Updated 4 months ago
• Kuree / fsim
  Fiber-based SystemVerilog Simulator.
  ☆25Updated 2 years ago
• sifive / block-pio-sifive
  An example of on-boarding a PIO block in with duh and wake
  ☆12Updated 4 years ago
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆20Updated this week
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆35Updated 3 years ago
• CTSRD-CHERI / beri
  The BERI and CHERI processor and hardware platform
  ☆47Updated 7 years ago
• vegaluisjose / vast
  Verilog AST
  ☆21Updated last year
• cucapra / latte21
  Languages, Tools, and Techniques for Accelerator Design
  ☆33Updated 3 years ago
• SRI-CSL / l3riscv
  An executable specification of the RISCV ISA in L3.
  ☆41Updated 5 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆35Updated 10 months ago
• SymbioticEDA / nerv
  Naive Educational RISC-V -- A simple single-stage RV32I processor
  ☆25Updated 4 years ago
• CTSRD-CHERI / RVBS
  RISC-V BSV Specification
  ☆18Updated 5 years ago
• chipy-hdl / chipy
  chipy hdl
  ☆17Updated 6 years ago
• SiliconSemantics / firrtlator
  firrtlator is a FIRRTL C++ library
  ☆21Updated 8 years ago
• Coloquinte / quaigh
  Logic circuit analysis and optimization
  ☆30Updated 3 months ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆34Updated last year
• rdaly525 / coreir
  ☆102Updated 2 years ago
• chipsalliance / fpga-interchange-schema
  ☆52Updated 2 years ago
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆44Updated last year
• VLSIDA / OpenCache
  An open-source custom cache generator.
  ☆30Updated 10 months ago
• daniellustig / pipecheck
  ☆19Updated 10 years ago
• sifive / chisel-circt
  Library to compile Chisel circuits using LLVM/MLIR (CIRCT)
  ☆70Updated last year
• Kuree / kratos
  Debuggable hardware generator
  ☆67Updated last year
• gokhankici / iodine
  Iodine: Verifying Constant-Time Execution of Hardware
  ☆12Updated 3 years ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆51Updated this week
• rems-project / sail-arm
  Sail version of Arm ISA definition, currently for Armv9.3-A, and with the previous Sail Armv8.5-A model
  ☆74Updated this week
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆47Updated 2 weeks ago
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆56Updated this week