wzab / agwb
Support for automatic address map generation and address decoding logic for Wishbone connected hierachical systems
☆12Updated last year
Alternatives and similar repositories for agwb:
Users that are interested in agwb are comparing it to the libraries listed below
- VHDL related news.☆25Updated this week
- VHDL String Formatting Library☆24Updated 9 months ago
- VHDLproc is a VHDL preprocessor☆24Updated 2 years ago
- VHDL dependency analyzer☆23Updated 4 years ago
- GitHub-based statistics highlighting interesting facts about the HDL industry☆12Updated last year
- Standard and Curated cores, tested and working.☆11Updated 2 years ago
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆29Updated 3 weeks ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆41Updated 11 months ago
- Interfacing VHDL and foreign languages with VUnit☆14Updated 5 years ago
- Example of Test Driven Design with VUnit☆14Updated 3 years ago
- VHDL plugin for RgGen☆11Updated this week
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.☆14Updated 2 weeks ago
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Updated 3 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆42Updated 2 years ago
- Interface definitions for VHDL-2019.☆12Updated last year
- ☆20Updated 4 years ago
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆47Updated this week
- Examples and design pattern for VHDL verification☆15Updated 8 years ago
- Open Source Verification Bundle for VHDL and System Verilog☆43Updated last year
- A VHDL Core Library.☆17Updated 7 years ago
- ☆21Updated 6 months ago
- GHDL C extensions☆11Updated 5 years ago
- Playing around with Formal Verification of Verilog and VHDL☆54Updated 4 years ago
- Generator for VHDL regular expression matchers☆14Updated 4 years ago
- VUnit GitHub action☆15Updated 3 years ago
- ☆13Updated 2 months ago
- A translation of the Xilinx XPM library to VHDL for simulation purposes☆52Updated 4 months ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆65Updated 2 weeks ago