davidharrishmc / cvw
Configurable RISC-V Processor
☆21Updated this week
Alternatives and similar repositories for cvw:
Users that are interested in cvw are comparing it to the libraries listed below
- FLIX-V: FPGA, Linux and RISC-V☆41Updated last year
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆43Updated last year
- A pipelined RISC-V processor☆50Updated last year
- ☆19Updated 6 months ago
- CologneChip GateMate FPGA Module: GMM-7550☆21Updated last year
- sump3 logic analyzer☆18Updated last month
- KiCad symbol library for sky130 and gf180mcu PDKs☆30Updated last year
- FPGA examples on Google Colab☆19Updated 10 months ago
- Demonstration of the YoWASP toolchain being used with Visual Studio Code to program a Radiona ULX3S board☆11Updated last year
- Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker☆96Updated last year
- Demo projects for various Kintex FPGA boards☆50Updated 8 months ago
- Experimental flows using nextpnr for Xilinx devices☆41Updated 2 weeks ago
- This repository contains small example designs that can be used with the open source icestorm flow.☆143Updated 3 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆49Updated last month
- ☆14Updated 2 months ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆87Updated 5 months ago
- Doom classic port to lightweight RISC‑V☆87Updated 2 years ago
- ☆44Updated 2 years ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆52Updated this week
- Example Verilog code for Ulx3s☆40Updated 2 years ago
- ☆63Updated 6 months ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆84Updated 6 years ago
- Another size-optimized RISC-V CPU for your consideration.☆58Updated last week
- ☆59Updated 3 years ago
- RISC-V Processor written in Amaranth HDL☆36Updated 3 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆37Updated 9 months ago
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆94Updated 6 months ago
- Virtual Development Board☆58Updated 3 years ago
- RISC-V Playground on Nandland Go☆16Updated last year
- Miscellaneous ULX3S examples (advanced)☆75Updated 3 weeks ago