davidharrishmc / cvwLinks
Configurable RISC-V Processor
☆21Updated 3 weeks ago
Alternatives and similar repositories for cvw
Users that are interested in cvw are comparing it to the libraries listed below
Sorting:
- RISC-V Processor written in Amaranth HDL☆39Updated 3 years ago
- A pipelined RISC-V processor☆57Updated last year
- Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker☆100Updated 2 years ago
- FLIX-V: FPGA, Linux and RISC-V☆42Updated last year
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 3 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆98Updated 2 weeks ago
- ☆70Updated 11 months ago
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆88Updated last month
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆47Updated last year
- Doom classic port to lightweight RISC‑V☆94Updated 3 years ago
- Virtual Development Board☆60Updated 3 years ago
- Collection of projects for various FPGA development boards☆45Updated last year
- New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi…☆99Updated last year
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆107Updated last year
- Demonstration of the YoWASP toolchain being used with Visual Studio Code to program a Radiona ULX3S board☆11Updated last year
- KiCad symbol library for sky130 and gf180mcu PDKs☆32Updated last year
- FPGA Odysseus with ULX3S☆66Updated last year
- Miscellaneous ULX3S examples (advanced)☆78Updated last month
- Another size-optimized RISC-V CPU for your consideration.☆58Updated 3 weeks ago
- Demo projects for various Kintex FPGA boards☆60Updated 2 months ago
- Example Verilog code for Ulx3s☆41Updated 3 years ago
- Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board☆23Updated 3 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆91Updated 7 years ago
- Portable HyperRAM controller☆56Updated 8 months ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- Experimental flows using nextpnr for Xilinx devices☆49Updated 2 months ago
- ☆20Updated 4 years ago
- Use ECP5 JTAG port to interact with user design☆31Updated 4 years ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆66Updated last week
- RISC-V CPU implementation in Amaranth HDL (aka nMigen)☆31Updated 11 months ago