A simple digital waveform viewer with vi-like key bindings.
☆144Mar 7, 2025Updated 11 months ago
Alternatives and similar repositories for dwfv
Users that are interested in dwfv are comparing it to the libraries listed below
Sorting:
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Jul 7, 2022Updated 3 years ago
- PicoRV☆43Feb 19, 2020Updated 6 years ago
- Rust proof-of-concept for GPU waveform rendering☆13Jul 22, 2020Updated 5 years ago
- download the macOS SDK legally without an Apple account☆11Jun 1, 2023Updated 2 years ago
- Read and write VCD (Value Change Dump) files in Rust☆45Feb 27, 2024Updated 2 years ago
- Experiments with Yosys cxxrtl backend☆50Jan 16, 2025Updated last year
- Finding the bacteria in rotting FPGA designs.☆14Dec 28, 2020Updated 5 years ago
- converts catgirls to gds files☆15May 24, 2021Updated 4 years ago
- ☆16Jun 13, 2021Updated 4 years ago
- Bulk scrape and download datasheets from various vendors (insult)☆14Aug 10, 2021Updated 4 years ago
- WebAssembly-based Yosys distribution for Amaranth HDL☆29Feb 25, 2026Updated last week
- Hot Reconfiguration Technology demo☆42Aug 23, 2022Updated 3 years ago
- Verilog based simulation modell for 7 Series PLL☆17May 4, 2020Updated 5 years ago
- A Binary Ninja plugin providing a set of BinaryViews for loading Motorola SREC, Intel HEX, and TI-TXT "hex" files☆10Sep 5, 2024Updated last year
- Cache & In-Memory optimizations for Rust, revived from the slabs of Sumer.☆30Feb 22, 2020Updated 6 years ago
- memory-mapped registers for x86_64 systems☆37May 18, 2021Updated 4 years ago
- Building and deploying container images for open source electronic design automation (EDA)☆121Oct 3, 2024Updated last year
- Resource-efficient 16-bit CPU architecture for FPGA control plane☆96Feb 20, 2025Updated last year
- Industry standard I/O for nMigen☆12Apr 23, 2020Updated 5 years ago
- Hardware generator debugger☆77Feb 12, 2024Updated 2 years ago
- converts ValueChangeDump-Files (vcd) to tikz-timing-diagrams☆16Nov 19, 2021Updated 4 years ago
- VCD file (Value Change Dump) command line viewer☆120Nov 9, 2025Updated 3 months ago
- Open source hardware down to the chip level!☆30Sep 24, 2021Updated 4 years ago
- An experiment for building gateware for the axiom micro / beta using amaranth-hdl☆45May 25, 2025Updated 9 months ago
- Reduced Embeddable More Or Less Tcl☆11Feb 6, 2025Updated last year
- Sticky sticky PCI☆10Oct 25, 2018Updated 7 years ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆31Dec 6, 2021Updated 4 years ago
- Documenting Lattice's 28nm FPGA parts☆149Feb 26, 2026Updated last week
- HDL development environment on Nix.☆26Oct 23, 2024Updated last year
- A SystemVerilog Language Server☆194Nov 30, 2025Updated 3 months ago
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆32Jan 30, 2025Updated last year
- SystemVerilog linter☆377Nov 6, 2025Updated 4 months ago
- Low Level Hardware Description — A foundation for building hardware design tools.☆427Apr 20, 2022Updated 3 years ago
- An experimental package manager and development tool for Hardware Description Languages (HDL).☆14Apr 10, 2022Updated 3 years ago
- Ruby Hardware Description Language☆15Mar 13, 2013Updated 12 years ago
- A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.☆50Dec 30, 2024Updated last year
- A usable language reference for VHDL that is concise, direct, and easy to understand.☆26Sep 16, 2025Updated 5 months ago
- SystemVerilog language server☆563Feb 20, 2026Updated 2 weeks ago
- Verilator Porcelain☆49Nov 7, 2023Updated 2 years ago