chipsalliance / verilator
Verilator open-source SystemVerilog simulator and lint system
☆35Updated last month
Related projects ⓘ
Alternatives and complementary repositories for verilator
- Generic FIFO implementation with optional FWFT☆54Updated 4 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆59Updated 3 years ago
- SystemVerilog modules and classes commonly used for verification☆44Updated 4 months ago
- pulp_soc is the core building component of PULP based SoCs☆78Updated 3 months ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆54Updated 3 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆58Updated last month
- ☆75Updated last year
- A look ahead, round-robing parametrized arbiter written in Verilog.☆40Updated 4 years ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆56Updated 3 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆81Updated 6 months ago
- Generic Register Interface (contains various adapters)☆100Updated last month
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆25Updated 4 years ago
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆29Updated 5 months ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆58Updated 4 years ago
- Simple single-port AXI memory interface☆36Updated 5 months ago
- RTL Verilog library for various DSP modules☆83Updated 2 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆63Updated 7 months ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆79Updated last month
- Standard Cell Library based Memory Compiler using FF/Latch cells☆133Updated 5 months ago
- Home of the Advanced Interface Bus (AIB) specification.☆49Updated 2 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 2 years ago
- Connecting SystemC with SystemVerilog☆36Updated 12 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆146Updated this week
- ideas and eda software for vlsi design☆47Updated this week
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆129Updated 2 weeks ago
- RISC-V Verification Interface☆76Updated 2 months ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆28Updated 4 months ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆127Updated last month
- Ethernet MAC 10/100 Mbps☆79Updated 5 years ago