black-parrot / black-parrot-sim
☆12Updated 2 months ago
Alternatives and similar repositories for black-parrot-sim:
Users that are interested in black-parrot-sim are comparing it to the libraries listed below
- HLS for Networks-on-Chip☆33Updated 4 years ago
- ☆24Updated 5 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- Advanced Architecture Labs with CVA6☆54Updated last year
- ☆29Updated 5 years ago
- ☆25Updated last year
- An Open-Hardware CGRA for accelerated computation on the edge.☆16Updated 5 months ago
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆14Updated 9 months ago
- A low power platform based on X-HEEP and integrating the ESL-CGRA☆13Updated 4 months ago
- A verilog implementation for Network-on-Chip☆71Updated 7 years ago
- Project repo for the POSH on-chip network generator☆43Updated last year
- ☆41Updated 6 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆48Updated 7 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆19Updated 4 months ago
- Development of a Network on Chip Simulation using SystemC.☆31Updated 7 years ago
- Ratatoskr NoC Simulator☆24Updated 3 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆68Updated 3 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆61Updated last year
- Pure digital components of a UCIe controller☆55Updated this week
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆38Updated 5 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆50Updated this week
- This is a tutorial on standard digital design flow☆73Updated 3 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆28Updated 4 months ago
- SystemVerilog Functional Coverage for RISC-V ISA☆25Updated 4 months ago
- Public release☆49Updated 5 years ago
- Dataset for ML-guided Accelerator Design☆34Updated 3 months ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆75Updated 10 months ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆36Updated 2 years ago
- The open-sourced version of BOOM-Explorer☆36Updated last year