black-parrot / black-parrot-sim

Related projects: ⓘ

• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆27Updated 3 years ago
• hyoukjun / OpenSMART
  Public release
  ☆45Updated 5 years ago
• hyoukjun / microswitch-noc
  ☆21Updated 4 years ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆45Updated 4 years ago
• Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulator
  An example of using Ramulator as memory model in a cycle-accurate SystemC Design
  ☆44Updated 7 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆38Updated 4 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆35Updated 2 years ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆60Updated 6 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆43Updated 3 months ago
• kuladeepsaireddy / OpenNoc
  ☆24Updated 5 years ago
• riscv-stc / riscv-matrix-spec
  RISC-V Matrix Specification
  ☆14Updated last week
• cornell-brg / pymtl3-net
  Project repo for the POSH on-chip network generator
  ☆41Updated last year
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆30Updated last year
• pulp-platform / fpu
  ☆35Updated 5 years ago
• chipsalliance / aib-protocols
  ☆22Updated 7 months ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆48Updated last month
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆43Updated 8 months ago
• bojackchen / digital-flow
  This is a tutorial on standard digital design flow
  ☆71Updated 3 years ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆60Updated 2 years ago
• amin-norollah / PAT-Noxim
  cycle accurate Network-on-Chip Simulator
  ☆24Updated last year
• riscv-stc / riscv-matrix-project
  Top project for RISC-V Matrix extension proposal and related opensource implementations.
  ☆22Updated 5 months ago
• PrincetonUniversity / smappic
  ☆19Updated last year
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆63Updated 9 years ago
• harvard-acc / ESP_Systolic_Array_Accelerator
  ☆3Updated 3 years ago
• jmjos / ratatoskr
  Ratatoskr NoC Simulator
  ☆18Updated 3 years ago
• ReuelReuben / vsdSRAM
  SRAM
  ☆19Updated 4 years ago
• hlslibs / ac_ml
  Algorithmic C Machine Learning Library
  ☆20Updated last month
• UT-LCA / ML4Accel-Dataset
  Dataset for ML-guided Accelerator Design
  ☆30Updated 5 months ago
• debtanu09 / systolic_array_matrix_multiplier
  This is a verilog implementation of 4x4 systolic array multiplier
  ☆29Updated 3 years ago
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆39Updated 3 years ago