black-parrot / black-parrot-simLinks
☆12Updated 3 months ago
Alternatives and similar repositories for black-parrot-sim
Users that are interested in black-parrot-sim are comparing it to the libraries listed below
Sorting:
- Project repo for the POSH on-chip network generator☆52Updated 9 months ago
- HLS for Networks-on-Chip☆39Updated 4 years ago
- Public release☆58Updated 6 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆55Updated 8 years ago
- ☆28Updated 6 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated last month
- Ratatoskr NoC Simulator☆29Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆77Updated last month
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆62Updated 4 years ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- Advanced Architecture Labs with CVA6☆72Updated last year
- Development of a Network on Chip Simulation using SystemC.☆33Updated 8 years ago
- A toolchain for rapid design space exploration of chiplet architectures☆71Updated 5 months ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆74Updated 6 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- BlackParrot on Zynq☆47Updated 3 weeks ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆48Updated 3 weeks ago
- An integrated CGRA design framework☆91Updated 9 months ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆60Updated 3 weeks ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Updated last month
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆70Updated 2 years ago
- ☆40Updated 6 years ago
- The open-sourced version of BOOM-Explorer☆46Updated 2 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Updated 3 years ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- ☆33Updated last month
- eyeriss-chisel3☆40Updated 3 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆149Updated last week
- ☆57Updated 6 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago