black-parrot / black-parrot-simLinks
☆12Updated 2 months ago
Alternatives and similar repositories for black-parrot-sim
Users that are interested in black-parrot-sim are comparing it to the libraries listed below
Sorting:
- Public release☆58Updated 6 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆55Updated 8 years ago
- HLS for Networks-on-Chip☆38Updated 4 years ago
- Advanced Architecture Labs with CVA6☆71Updated last year
- Project repo for the POSH on-chip network generator☆52Updated 9 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆61Updated 4 years ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆71Updated 3 weeks ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆148Updated this week
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆73Updated 5 years ago
- This tools offer many simulation of memory design detail parameter. Then you can setting these parameter to running result in your condit…☆18Updated 9 years ago
- ☆28Updated 6 years ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- A toolchain for rapid design space exploration of chiplet architectures☆68Updated 4 months ago
- ☆57Updated 6 years ago
- Ratatoskr NoC Simulator☆29Updated 4 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated 2 weeks ago
- ☆65Updated 7 months ago
- An integrated CGRA design framework☆91Updated 9 months ago
- ☆46Updated last year
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 10 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆60Updated this week
- Development of a Network on Chip Simulation using SystemC.☆33Updated 8 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆47Updated this week
- ☆36Updated last month
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Updated 2 years ago
- ☆79Updated 11 years ago
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆38Updated 4 months ago