ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communication Framework) ChipScope Server (cs_server).
☆76Jul 1, 2026Updated 3 months ago
Alternatives and similar repositories for chipscopy
Users that are interested in chipscopy are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Interfacing VHDL and foreign languages with VUnit☆15Feb 20, 2020Updated 6 years ago
- VHDL related news.☆27Updated this week
- Virtual development board for HDL design☆44Mar 31, 2023Updated 3 years ago
- VHDLproc is a VHDL preprocessor☆25May 12, 2022Updated 4 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆54Jun 5, 2022Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Library of reusable VHDL components☆28Mar 7, 2024Updated 2 years ago
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆22Oct 23, 2026Updated last week
- VHDL String Formatting Library☆27Apr 27, 2024Updated 2 years ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆70Feb 16, 2026Updated 8 months ago
- CLI tool for RTL design space exploration on top of Vivado☆15Jun 5, 2023Updated 3 years ago
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.☆14Updated this week
- GitHub-based statistics highlighting interesting facts about the HDL industry☆12Jul 6, 2023Updated 3 years ago
- Example of Test Driven Design with VUnit☆16Nov 22, 2021Updated 4 years ago
- RIFFA (Reusable Integration Framework for FPGA Accelerators) is a framework developed in University of California, San Diego. This projec…☆14Jul 16, 2015Updated 11 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- cryptography ip-cores in vhdl / verilog☆43Feb 20, 2021Updated 5 years ago
- Generator for VHDL regular expression matchers☆15Jan 11, 2021Updated 5 years ago
- Scripts to build and use docker images including GHDL☆45Nov 20, 2024Updated last year
- A VHDL Core Library.☆18Mar 29, 2017Updated 9 years ago
- Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware☆49Jul 24, 2024Updated 2 years ago
- vhdl related contents☆11Apr 27, 2020Updated 6 years ago
- A usable language reference for VHDL that is concise, direct, and easy to understand.☆26Jun 23, 2026Updated 4 months ago
- JavaScript action for users to easily install tip/nightly GHDL assets in GitHub Actions workflows☆16Jan 12, 2025Updated last year
- PYNQ Composabe Overlays☆81Jun 17, 2024Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- GHDL C extensions☆12Feb 20, 2020Updated 6 years ago
- PYNQ support and examples for Kria SOMs☆145Aug 12, 2026Updated 2 months ago
- ☆12May 29, 2020Updated 6 years ago
- Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or S…☆292Jun 4, 2026Updated 4 months ago
- The repository for the 2024 IEEE Cloud Submission of OS4C☆10Oct 22, 2026Updated last week
- FPGA config visualized. demo:☆20Mar 17, 2020Updated 6 years ago
- Hands-on experience programming AI Engines using Vitis Unified Software Platform☆43Jul 24, 2024Updated 2 years ago
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Jan 13, 2022Updated 4 years ago
- NPUEval is an LLM evaluation dataset written specifically to target AIE kernel code generation on RyzenAI hardware.☆34Nov 8, 2025Updated 11 months ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Streaming based VHDL parser.☆86Updated this week
- The Demo that was presented at FCCM.☆16Aug 16, 2018Updated 8 years ago
- A wrapper for GHDL to make it look like Mentor's ModelSim. Helpful for use with programs like Sigasi.☆11Jan 21, 2018Updated 8 years ago
- A VHDL implementation of 128 bit AES encryption with a PCIe interface.☆27Jan 9, 2017Updated 9 years ago
- A translation of the Xilinx XPM library to VHDL for simulation purposes☆71Jul 29, 2026Updated 3 months ago
- Build Customized FPGA Implementations for Vivado☆395Updated this week
- An abstraction library for interfacing EDA tools☆802Sep 15, 2026Updated last month