Alternatives and similar repositories for chipscopy

Users that are interested in chipscopy are comparing it to the libraries listed below

• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆76Updated 3 months ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆81Updated 3 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆38Updated 2 weeks ago
• antmicro / cocotb-verilator-build
  ☆26Updated 2 years ago
• wyvernSemi / vproc
  Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
  ☆69Updated last month
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 6 months ago
• mohamed / fsm2sv
  SystemVerilog FSM generator
  ☆32Updated last year
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆41Updated 4 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆50Updated last year
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆79Updated last week
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆60Updated 2 years ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆57Updated last month
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆48Updated last year
• antmicro / verilator-verification
  Test dashboard for verification features in Verilator
  ☆28Updated this week
• Digilent / digilent-vivado-scripts
  ☆69Updated 3 months ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆54Updated last year
• verilator / example-systemverilog
  ☆40Updated last year
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆86Updated 5 years ago
• suoto / fpga_cores
  ☆33Updated 2 years ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆55Updated 5 years ago
• accellera-official / PySysC
  Public repository for PySysC, (From SC Common Practices Subgroup)
  ☆54Updated last year
• Nic30 / pyDigitalWaveTools
  Python library for operations with VCD and other digital wave files
  ☆53Updated last week
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆30Updated last year
• CospanDesign / python-pci
  Python interface to PCIE
  ☆40Updated 7 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆34Updated 9 months ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆23Updated last year
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆51Updated last week
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆75Updated 2 weeks ago