edaa-org / pyEDAA.ReportsLinks
Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.
☆14Updated last week
Alternatives and similar repositories for pyEDAA.Reports
Users that are interested in pyEDAA.Reports are comparing it to the libraries listed below
Sorting:
- VHDL related news.☆27Updated this week
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Updated 4 years ago
- Unified Coverage Interoperability Standard (UCIS)☆13Updated last week
- VHDL plugin for RgGen☆15Updated last week
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆32Updated 11 months ago
- Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.☆13Updated 3 months ago
- VHDLproc is a VHDL preprocessor☆24Updated 3 years ago
- ☆24Updated 9 months ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆42Updated last year
- VHDL String Formatting Library☆26Updated last year
- A VHDL Core Library.☆18Updated 8 years ago
- Generate symbols from HDL components/modules☆22Updated 2 years ago
- GitHub-based statistics highlighting interesting facts about the HDL industry☆12Updated 2 years ago
- Open Source Verification Bundle for VHDL and System Verilog☆48Updated 2 years ago
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆28Updated 2 months ago
- VHDL dependency analyzer☆24Updated 5 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆49Updated 3 years ago
- Standard and Curated cores, tested and working.☆11Updated 3 years ago
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆26Updated 4 years ago
- JavaScript action for users to easily install tip/nightly GHDL assets in GitHub Actions workflows☆16Updated last year
- Deprecated - This library has been replaced by OsvvmLibraries. The links to the submodules will not be updated to the new versions.☆10Updated 5 years ago
- A translation of the Xilinx XPM library to VHDL for simulation purposes☆60Updated 2 months ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated 11 months ago
- Generator for VHDL regular expression matchers☆15Updated 5 years ago
- ☆20Updated 5 years ago
- Import and export IP-XACT XML register models☆36Updated 2 months ago
- Cross EDA Abstraction and Automation☆40Updated 2 months ago
- Interfacing VHDL and foreign languages with VUnit☆15Updated 5 years ago
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆51Updated this week
- IP-XACT XML binding library☆16Updated 9 years ago