edaa-org / pyEDAA.Reports
Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.
☆13Updated this week
Related projects: ⓘ
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Updated 2 years ago
- VHDL plugin for RgGen☆11Updated 3 months ago
- VHDL related news.☆24Updated this week
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆27Updated this week
- Interfacing VHDL and foreign languages with VUnit☆14Updated 4 years ago
- Example of Test Driven Design with VUnit☆12Updated 2 years ago
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆20Updated 9 months ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆41Updated 6 months ago
- GitHub-based statistics highlighting interesting facts about the HDL industry☆11Updated last year
- VHDL String Formatting Library☆23Updated 4 months ago
- VHDLproc is a VHDL preprocessor☆25Updated 2 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆13Updated 5 months ago
- A VHDL Core Library.☆17Updated 7 years ago
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆21Updated 3 years ago
- Open Source Verification Bundle for VHDL and System Verilog☆39Updated 8 months ago
- ☆10Updated this week
- VHDL dependency analyzer☆21Updated 4 years ago
- Standard and Curated cores, tested and working.☆11Updated last year
- Specification of the Wishbone SoC Interconnect Architecture☆40Updated 2 years ago
- ☆20Updated last month
- Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.☆12Updated 2 years ago
- ☆19Updated 4 years ago
- Examples and design pattern for VHDL verification☆15Updated 8 years ago
- Provides automation scripts for building BFMs☆15Updated 2 years ago
- Making cocotb testbenches that bit easier☆18Updated last week
- Generator for VHDL regular expression matchers☆13Updated 3 years ago
- Support for automatic address map generation and address decoding logic for Wishbone connected hierachical systems☆12Updated 9 months ago
- IP-XACT XML binding library☆13Updated 8 years ago
- Python/Simulator integration using procedure calls☆9Updated 4 years ago
- Python interface for cross-calling with HDL☆13Updated 3 weeks ago