TerosTechnology / teroshdl-documenter-demoView external linksLinks
This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.
☆10Jan 13, 2022Updated 4 years ago
Alternatives and similar repositories for teroshdl-documenter-demo
Users that are interested in teroshdl-documenter-demo are comparing it to the libraries listed below
Sorting:
- Standard and Curated cores, tested and working.☆11Dec 29, 2022Updated 3 years ago
- VHDL related news.☆27Updated this week
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.☆14Jan 22, 2026Updated 3 weeks ago
- Interfacing VHDL and foreign languages with VUnit☆15Feb 20, 2020Updated 5 years ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆43Mar 7, 2024Updated last year
- Experiments with Cologne Chip's GateMate FPGA architecture☆17Nov 16, 2023Updated 2 years ago
- GitHub-based statistics highlighting interesting facts about the HDL industry☆12Jul 6, 2023Updated 2 years ago
- CLI tool for RTL design space exploration on top of Vivado☆15Jun 5, 2023Updated 2 years ago
- GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.☆16Apr 10, 2025Updated 10 months ago
- cryptography ip-cores in vhdl / verilog☆41Feb 20, 2021Updated 4 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆47Updated this week
- a project to check the FOSS synthesizers against vendors EDA tools☆12Sep 26, 2020Updated 5 years ago
- Generator for VHDL regular expression matchers☆15Jan 11, 2021Updated 5 years ago
- Example of Test Driven Design with VUnit☆16Nov 22, 2021Updated 4 years ago
- VHDLproc is a VHDL preprocessor☆24May 12, 2022Updated 3 years ago
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆51Updated this week
- Fixed point package for Python.☆36Apr 28, 2023Updated 2 years ago
- A translation of the Xilinx XPM library to VHDL for simulation purposes☆63Nov 7, 2025Updated 3 months ago
- Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.☆13Sep 22, 2025Updated 4 months ago
- VHDL dependency analyzer☆24Mar 10, 2020Updated 5 years ago
- Building and deploying container images for open source electronic design automation (EDA)☆120Oct 3, 2024Updated last year
- Virtual development board for HDL design☆42Mar 31, 2023Updated 2 years ago
- Support for automatic address map generation and address decoding logic for Wishbone connected hierachical systems☆12Updated this week
- ASCII art figures can be parsed and output as SVG, PNG, JPEG, PDF and more. This project provides a python package and a command line scr…☆21Jul 5, 2017Updated 8 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆51Jun 5, 2022Updated 3 years ago
- RISCV CPU implementation tutorial steps for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga☆14Feb 26, 2025Updated 11 months ago
- A first approach of getting a pure Ada program running on an FPGA with SaxonSOC☆11Apr 12, 2021Updated 4 years ago
- VUnit and Cocotb Smashed Together☆15May 31, 2024Updated last year
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Feb 2, 2025Updated last year
- Drop In USB CDC ACM core for iCE40 FPGA☆34Sep 5, 2021Updated 4 years ago
- This repository is an excuse to learn about Convolutional Neural Networks by implementing one in FPGA. The main goal is to learn, and to …☆12Jul 12, 2020Updated 5 years ago
- ulx3s ghdl examples☆15Mar 6, 2021Updated 4 years ago
- Library of reusable VHDL components☆28Mar 7, 2024Updated last year
- cocotb code library☆13Dec 28, 2020Updated 5 years ago
- JavaScript action for users to easily install tip/nightly GHDL assets in GitHub Actions workflows☆16Jan 12, 2025Updated last year
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆32Jan 30, 2025Updated last year
- A linux'ish build system for System on Chip designs, based on GHDL☆12Dec 14, 2024Updated last year
- ☆33Apr 30, 2023Updated 2 years ago