Alternatives and similar repositories for sphinxcontrib-hdl-diagrams

Users that are interested in sphinxcontrib-hdl-diagrams are comparing it to the libraries listed below

• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆81Updated 3 years ago
• VHDL / pyVHDLModel
  An abstract language model of VHDL written in Python.
  ☆57Updated last week
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆72Updated last year
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆43Updated this week
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• os-fpga / FOEDAG
  Framework Open EDA Gui
  ☆73Updated 11 months ago
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆51Updated this week
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆70Updated last month
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆57Updated 2 months ago
• cirosantilli / vcdvcd
  Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
  ☆64Updated 3 weeks ago
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆65Updated last year
• Nic30 / pyDigitalWaveTools
  Python library for operations with VCD and other digital wave files
  ☆53Updated this week
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆160Updated last week
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆48Updated 3 years ago
• aignacio / nox
  RISC-V Nox core
  ☆68Updated 3 months ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 9 months ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆62Updated this week
• hdl / containers
  Building and deploying container images for open source electronic design automation (EDA)
  ☆115Updated last year
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆76Updated 3 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆148Updated 5 months ago
• antmicro / verilator-verification
  Test dashboard for verification features in Verilator
  ☆28Updated this week
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆76Updated 3 weeks ago
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆48Updated last year
• FPGA-Systems / drawio-hdl-builder
  Drawio => VHDL and Verilog
  ☆61Updated 2 years ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆119Updated 2 years ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆62Updated 4 years ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆117Updated 4 years ago
• bluecheetah / bag
  BAG framework
  ☆41Updated last year
• stineje / sky130RHBDlib
  Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130
  ☆10Updated 5 months ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago