Alternatives and similar repositories for sphinxcontrib-hdl-diagrams:

Users that are interested in sphinxcontrib-hdl-diagrams are comparing it to the libraries listed below

• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆145Updated last week
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆74Updated this week
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆80Updated 9 months ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆75Updated 2 years ago
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆51Updated last year
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆55Updated 2 months ago
• accellera-official / PySysC
  Public repository for PySysC, (From SC Common Practices Subgroup)
  ☆51Updated last year
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆73Updated this week
• VHDL / pyVHDLModel
  An abstract language model of VHDL written in Python.
  ☆50Updated this week
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆33Updated 3 months ago
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆54Updated this week
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆36Updated this week
• aignacio / nox
  RISC-V Nox core
  ☆62Updated 6 months ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆44Updated this week
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆71Updated 7 months ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆54Updated 4 months ago
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆36Updated 3 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 5 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆126Updated 3 weeks ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆48Updated 5 months ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆55Updated last month
• mohamed / fsm2sv
  SystemVerilog FSM generator
  ☆27Updated 9 months ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆52Updated last week
• os-fpga / FOEDAG
  Framework Open EDA Gui
  ☆63Updated 2 months ago
• wyvernSemi / vproc
  Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
  ☆52Updated last week
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆112Updated 2 months ago
• bluecheetah / bag
  BAG framework
  ☆40Updated 6 months ago
• sgherbst / svreal
  Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
  ☆43Updated 4 years ago
• Nic30 / pyDigitalWaveTools
  Python library for operations with VCD and other digital wave files
  ☆47Updated 8 months ago