Alternatives and similar repositories for DE10-GPU

Users that are interested in DE10-GPU are comparing it to the libraries listed below

• pulp-platform / trace_debugger
  Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.
  ☆19Updated last year
• franzflasch / leiwand_rv32
  RISC-V RV32I CPU written in verilog
  ☆10Updated 5 years ago
• bharathk005 / Verilog_projects
  HDMI + GPU-pipeline + FFT
  ☆14Updated 9 years ago
• openhwgroup / cv32e40x-dv
  CV32E40X Design-Verification environment
  ☆14Updated last year
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆27Updated 2 years ago
• himanshu5-prog / vortexGPU
  ☆22Updated 4 years ago
• b224hisl / rioschip
  ☆32Updated 2 years ago
• ecilasun / e32e
  Latest in the line of the E32 processors with better/generic cache placement
  ☆10Updated 2 years ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆34Updated this week
• bluespec / RISCV_gdbstub
  A gdbstub for connecting GDB to a RISC-V Debug Module
  ☆30Updated last year
• felsabbagh3 / Vortex
  RISC-V GPGPU
  ☆35Updated 5 years ago
• jbush001 / ChiselGPU
  Experiments with fixed function renderers and Chisel HDL
  ☆59Updated 6 years ago
• mjkkirschner / simpleGPUCore
  verilog/FPGA hardware description for very simple GPU
  ☆17Updated 6 years ago
• sabbaghm / c-ll-verilog
  An LLVM based mini-C to Verilog High-level Synthesis tool
  ☆39Updated 7 months ago
• enjoy-digital / pcie_analyzer
  PCIe analyzer experiments
  ☆63Updated 5 years ago
• riscv / riscv-test-env
  ☆50Updated last month
• leonardt / verilogAST-cpp
  C++17 implementation of an AST for Verilog code generation
  ☆24Updated 2 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆55Updated 7 months ago
• RSPwFPGAs / qemu-hdl-cosim
  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
  ☆49Updated 4 years ago
• SymbioticEDA / getting-started-FV
  ☆18Updated 5 years ago
• Pufferfish / tlm-of-a-pcie-rootcomplex-systemc
  A transaction level model of a PCI express root complex implemented in systemc
  ☆23Updated 11 years ago
• tomverbeure / gdbwave
  GDB server to debug CPU simulation waveform traces
  ☆43Updated 3 years ago
• riscv-admin / riscv-ovpsim
  ☆61Updated 4 years ago
• rochus-keller / Verilog
  This is the Verilog 2005 parser used by VerilogCreator
  ☆15Updated 6 years ago
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆97Updated 6 months ago
• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆39Updated last year
• freecores / sparc64soc
  OpenSPARC-based SoC
  ☆71Updated 11 years ago
• edgarigl / qemu-etrace
  Qemu Etrace
  ☆15Updated last year
• intel / pfr-wilson-city
  ☆24Updated last month
• OpenCAPI / omi_device_ice
  An example OMI Device FPGA with 2 DDR4 memory ports
  ☆18Updated 2 years ago