CMU-SAFARI / Load-InspectorLinks
A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program. Described by Bera et al. in https://arxiv.org/pdf/2406.18786
☆23Updated last year
Alternatives and similar repositories for Load-Inspector
Users that are interested in Load-Inspector are comparing it to the libraries listed below
Sorting:
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆33Updated last year
- Heterogeneous simulator for DECADES Project☆32Updated last year
- Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …☆17Updated 4 years ago
- ☆26Updated 2 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- A fast, accurate, and easy-to-integrate memory simulator that model memory system performance with bandwidth--latency curves.☆32Updated 2 months ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 3 years ago
- A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…☆76Updated 3 months ago
- A simulator integrates ChampSim and Ramulator.☆19Updated 4 months ago
- Artifact for "DX100: A Programmable Data Access Accelerator for Indirection (ISCA 2025)" paper☆14Updated last month
- ☆22Updated last month
- Championship Value Prediction (CVP) simulator.☆17Updated 4 years ago
- The gem5-X open source framework (based on the gem5 simulator)☆42Updated 2 years ago
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆24Updated 3 weeks ago
- ☆108Updated last year
- ☆40Updated 8 months ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆70Updated 2 years ago
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆46Updated 6 months ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- Implementing the Precise Runahead (HPCA'20) in gem5☆13Updated 2 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆45Updated 11 months ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆45Updated 8 years ago
- ☆17Updated 2 months ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- Qemu tracing plugin using SimPoints☆17Updated last year
- ☆52Updated 11 months ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆40Updated 6 years ago
- STONNE Simulator integrated into SST Simulator☆22Updated last year
- Processing in Memory Emulation☆22Updated 2 years ago