Alternatives and similar repositories for S64X7

Users that are interested in S64X7 are comparing it to the libraries listed below

• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated 2 years ago
• knielsen / ice40_viewer
  ☆61Updated last year
• stacksmith / fpgasm
  FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)
  ☆53Updated 4 years ago
• ZipCPU / zbasic
  A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
  ☆43Updated 2 years ago
• pepijndevos / seqpu
  A bit-serial CPU
  ☆19Updated 5 years ago
• haojunliu / OpenFPGA
  OpenFPGA
  ☆34Updated 7 years ago
• SteffenReith / J1Sc
  A reimplementation of a tiny stack CPU
  ☆85Updated last year
• cseed / cynth
  a simple C-to-Verilog compiler
  ☆51Updated 8 years ago
• mballance / fwrisc-s
  ☆10Updated 5 years ago
• whitequark / Boneless-CPU
  Resource-efficient 16-bit CPU architecture for FPGA control plane
  ☆96Updated 6 months ago
• JohnDRO / Golirev-IDE
  An online Verilog IDE based on YosysJS.
  ☆24Updated 9 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• OpenCAPI / omi_device_ice
  An example OMI Device FPGA with 2 DDR4 memory ports
  ☆18Updated 2 years ago
• hamsternz / emulate-risc-v
  A very simple RISC-V ISA emulator.
  ☆38Updated 4 years ago
• mrisc32 / mrisc32
  MRSIC32 ISA documentation and development
  ☆90Updated 2 years ago
• cliffordwolf / icotools
  Tools and Examples for IcoBoard
  ☆81Updated 4 years ago
• CTSRD-CHERI / beri
  The BERI and CHERI processor and hardware platform
  ☆50Updated 8 years ago
• veripool / dinotrace
  Simulation VCD waveform viewer, using old Motif UI
  ☆27Updated 2 years ago
• ZipCPU / wbhyperram
  A cross platform, formally verified, open source, hyperRAM controller with simulator
  ☆11Updated 6 years ago
• laforest / Octavo
  Verilog FPGA Parts Library. Old Octavo soft-CPU project.
  ☆75Updated 6 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• RobertBaruch / n6800
  A 6800 CPU written in nMigen
  ☆49Updated 4 years ago
• tommythorn / yari
  YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includ…
  ☆46Updated 9 months ago
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆34Updated 5 months ago
• mrisc32 / mrisc32-a1
  A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA
  ☆24Updated 2 years ago
• Wren6991 / Hazard5
  5-stage RISC-V CPU, originally developed for RISCBoy
  ☆32Updated 2 years ago
• m-labs / nmigen-boards
  Board and connector definition files for nMigen
  ☆30Updated 4 years ago
• AngelTerrones / Algol
  A RISC-V CPU (Outdated: using priviledge v1.7)
  ☆25Updated 6 years ago
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆29Updated last week