Alternatives and similar repositories for S64X7

Users that are interested in S64X7 are comparing it to the libraries listed below

• pepijndevos / seqpu
  A bit-serial CPU
  ☆19Updated 5 years ago
• OpenCAPI / omi_device_ice
  An example OMI Device FPGA with 2 DDR4 memory ports
  ☆16Updated 2 years ago
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated 2 years ago
• veripool / dinotrace
  Simulation VCD waveform viewer, using old Motif UI
  ☆26Updated 2 years ago
• haojunliu / OpenFPGA
  OpenFPGA
  ☆33Updated 7 years ago
• mballance / fwrisc-s
  ☆10Updated 5 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• stacksmith / fpgasm
  FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)
  ☆53Updated 3 years ago
• hamsternz / emulate-risc-v
  A very simple RISC-V ISA emulator.
  ☆37Updated 4 years ago
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆34Updated last month
• j-core / jcore-cpu
  J-Core J2/J32 5 stage pipeline CPU core
  ☆52Updated 4 years ago
• jbush001 / MiteCPU
  Minimal microprocessor
  ☆20Updated 7 years ago
• drom / quark
  Stack CPU Work In Progress
  ☆30Updated last year
• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆28Updated 3 weeks ago
• mrisc32 / mrisc32-a1
  A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA
  ☆24Updated last year
• awygle / waggle
  Rust proof-of-concept for GPU waveform rendering
  ☆13Updated 4 years ago
• YosysHQ / yosys-plugins
  Yosys Plugins
  ☆21Updated 5 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• trabucayre / quickfeather-notes
  Notes, scripts and apps to quickfeather board
  ☆10Updated 3 years ago
• jamesbowman / sincos
  Efficient implementations of the transcendental functions
  ☆27Updated 8 years ago
• YosysHQ / prjtrellis-db
  Project Trellis database
  ☆13Updated last year
• defparam / higan-verilog
  This is a higan/Verilator co-simulation example/framework
  ☆50Updated 7 years ago
• JohnDRO / Golirev-IDE
  An online Verilog IDE based on YosysJS.
  ☆24Updated 9 years ago
• CTSRD-CHERI / beri
  The BERI and CHERI processor and hardware platform
  ☆50Updated 8 years ago
• lawrie / ulx3s_examples
  Example Verilog code for Ulx3s
  ☆40Updated 3 years ago
• zylin / zpugcc
  ☆51Updated 8 years ago
• ZipCPU / zbasic
  A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
  ☆43Updated 2 years ago
• lzw545 / opengg
  OpenGL-like graphics pipeline on a Xilinx FPGA
  ☆32Updated 14 years ago
• rob-ng15 / Silice-Playground
  Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice
  ☆35Updated last year
• tommythorn / yari
  YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includ…
  ☆45Updated 5 months ago