Alternatives and similar repositories for S64X7

Users that are interested in S64X7 are comparing it to the libraries listed below

• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated 2 years ago
• knielsen / ice40_viewer
  ☆61Updated 2 years ago
• stacksmith / fpgasm
  FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)
  ☆54Updated 4 years ago
• pepijndevos / seqpu
  A bit-serial CPU
  ☆19Updated 6 years ago
• mrisc32 / mrisc32-a1
  A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA
  ☆24Updated 2 years ago
• ZipCPU / zbasic
  A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
  ☆45Updated 3 years ago
• haojunliu / OpenFPGA
  OpenFPGA
  ☆34Updated 7 years ago
• mrisc32 / mrisc32
  MRSIC32 ISA documentation and development
  ☆91Updated 2 years ago
• mballance / fwrisc-s
  ☆10Updated 6 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• cseed / cynth
  a simple C-to-Verilog compiler
  ☆51Updated 8 years ago
• SteffenReith / J1Sc
  A reimplementation of a tiny stack CPU
  ☆86Updated 2 years ago
• OpenCAPI / omi_device_ice
  An example OMI Device FPGA with 2 DDR4 memory ports
  ☆20Updated 3 years ago
• j-core / jcore-cpu
  J-Core J2/J32 5 stage pipeline CPU core
  ☆61Updated 5 years ago
• defparam / higan-verilog
  This is a higan/Verilator co-simulation example/framework
  ☆51Updated 7 years ago
• whitequark / Boneless-CPU
  Resource-efficient 16-bit CPU architecture for FPGA control plane
  ☆96Updated 11 months ago
• hamsternz / emulate-risc-v
  A very simple RISC-V ISA emulator.
  ☆39Updated 5 years ago
• tommythorn / yari
  YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includ…
  ☆45Updated last year
• JohnDRO / Golirev-IDE
  An online Verilog IDE based on YosysJS.
  ☆24Updated 10 years ago
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆35Updated 2 months ago
• clairexen / picorv
  PicoRV
  ☆43Updated 5 years ago
• AngelTerrones / Algol
  A RISC-V CPU (Outdated: using priviledge v1.7)
  ☆26Updated 6 years ago
• libresilicon / qtflow
  Free open source EDA tools
  ☆66Updated 6 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated 2 weeks ago
• cliffordwolf / icotools
  Tools and Examples for IcoBoard
  ☆80Updated 4 years ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆50Updated last year
• combinatorylogic / soc
  An experimental System-on-Chip with a custom compiler toolchain.
  ☆60Updated 6 years ago
• tvanas / r-vex
  A reconfigurable and extensible VLIW processor implemented in VHDL
  ☆39Updated 10 years ago
• CTSRD-CHERI / beri
  The BERI and CHERI processor and hardware platform
  ☆50Updated 8 years ago
• tomverbeure / mr1
  MR1 formally verified RISC-V CPU
  ☆56Updated 7 years ago