xprova / netlist-graph

Related projects ⓘ

Alternatives and complementary repositories for netlist-graph

• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆17Updated 2 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• FPGA-Research-Manchester / eFPGA---RTL-to-GDS-with-SKY130
  This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
  ☆26Updated 3 years ago
• HardwareIR / netlistDB
  netlistDB - Intermediate format for digital hardware representation with graph database API
  ☆29Updated 3 years ago
• jinwookjungs / open_design_flow
  OpenDesign Flow Database
  ☆16Updated 6 years ago
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆28Updated last week
• StanfordVLSI / DaVE
  tools regarding on analog modeling, validation, and generation
  ☆21Updated last year
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆39Updated last year
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆31Updated 3 weeks ago
• b224hisl / rioschip
  ☆33Updated last year
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆43Updated last year
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆47Updated 9 years ago
• libresilicon / magic-8.2
  Magic VLSI Layout Tool
  ☆19Updated 5 years ago
• aolofsson / POSH
  ☆39Updated 4 years ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• parallella / openeda
  Open source EDA chip design flow
  ☆46Updated 7 years ago
• laurentc2 / ASAP7_for_KLayout
  KLayout technology files for ASAP7 FinFET educational process
  ☆18Updated last year
• scale-lab / PVTsensors
  Designs for Process-Voltage-Temperature (PVT) Sensors with MCU
  ☆21Updated 4 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆28Updated 4 months ago
• idea-fasoc / fasoc
  ☆52Updated last year
• thesourcerer8 / StdCellLib
  LibreSilicon's Standard Cell Library Generator
  ☆17Updated 6 months ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆22Updated 4 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆43Updated 4 months ago
• bluecheetah / bag
  BAG framework
  ☆41Updated 3 months ago
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆16Updated 2 months ago
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆46Updated 4 years ago
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆20Updated 2 years ago
• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆39Updated 4 years ago
• SymbioticEDA / getting-started-FV
  ☆18Updated 4 years ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆40Updated this week