Java library for parsing and manipulating graph representations of gate-level Verilog netlists
☆15Jan 9, 2017Updated 9 years ago
Alternatives and similar repositories for netlist-graph
Users that are interested in netlist-graph are comparing it to the libraries listed below
Sorting:
- OpenDesign Flow Database☆17Oct 31, 2018Updated 7 years ago
- A lightweight library to perform Python/Verilog co-simulation with Python3.3 coroutine + numpy. The name Nicotb cames from NatIve COrouti…☆21Dec 24, 2023Updated 2 years ago
- A standalone structural (gate-level) verilog parser☆40Feb 2, 2026Updated 3 weeks ago
- Libre Silicon Compiler☆22Apr 13, 2021Updated 4 years ago
- A copy of the latest version of MVSIS☆12Apr 18, 2021Updated 4 years ago
- The ANUBIS benchmark suite for Incremental Synthesis☆12Dec 15, 2020Updated 5 years ago
- BuDDy BDD package (with CMake support)☆15May 7, 2024Updated last year
- Verilog Plugin for Intellij IDEA☆10Oct 22, 2020Updated 5 years ago
- Handle Fast Signal Traces (fst) in Python☆14Jun 11, 2025Updated 8 months ago
- ☆16May 10, 2019Updated 6 years ago
- Approximate arithmetic circuits for FPGAs☆13Feb 19, 2020Updated 6 years ago
- Provides a packaged collection of open source EDA tools☆12Apr 14, 2019Updated 6 years ago
- This is a probabilistic SAT attack tool.☆13Jun 5, 2021Updated 4 years ago
- Cross EDA Abstraction and Automation☆41Nov 17, 2025Updated 3 months ago
- A synthesis flow for hybrid processing-in-RRAM modes☆12Jul 15, 2021Updated 4 years ago
- RISC-V BSV Specification☆23Jan 18, 2020Updated 6 years ago
- Python module containing verilog files for rocket cpu (for use with LiteX).☆14Jan 16, 2026Updated last month
- A Standalone Structural Verilog Parser☆99Mar 31, 2022Updated 3 years ago
- A flexible framework for analyzing and transforming FPGA netlists. Official repository.☆106Feb 12, 2025Updated last year
- A Matlab/Octave parser implemented in Python, using the Lex-Yacc framework.☆18Sep 13, 2021Updated 4 years ago
- The PE for the second generation CGRA (garnet).☆18Feb 22, 2026Updated last week
- Fast PnR toolchain for CGRA☆18Jul 26, 2024Updated last year
- SAT-based ATPG using TG-Pro model☆19Jun 5, 2018Updated 7 years ago
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆18Jul 17, 2016Updated 9 years ago
- ☆17Nov 19, 2023Updated 2 years ago
- libCircuit is a C++ Library for EDA software development☆18Sep 27, 2018Updated 7 years ago
- Cross platform Instant Outbidding Bot, Instant Outbidder Bot is designed to outbid all real-time bids within a second by percentage incre…☆100Jan 17, 2023Updated 3 years ago
- Verilog parsing and generator crate.☆21Apr 16, 2020Updated 5 years ago
- ☆19Aug 30, 2020Updated 5 years ago
- DATC Robust Design Flow.☆35Jan 21, 2020Updated 6 years ago
- ☆24Feb 15, 2013Updated 13 years ago
- Contains examples to start with Kactus2.☆23Aug 5, 2024Updated last year
- A verilog parser☆19Apr 12, 2024Updated last year
- LLVM based HLS library for HWToolkit (hardware devel. toolkit)☆27Jan 21, 2026Updated last month
- ☆21Jan 25, 2018Updated 8 years ago
- Python wrapper for verilator model☆93Feb 10, 2024Updated 2 years ago
- IP-core package generator for AXI4/Avalon☆22Nov 25, 2018Updated 7 years ago
- A Verilog parser for Haskell.☆36Jul 6, 2021Updated 4 years ago
- InfiniTAM on FPGA☆26Jul 11, 2019Updated 6 years ago