Alternatives and similar repositories for netlist-graph

Users that are interested in netlist-graph are comparing it to the libraries listed below

• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆29Updated 3 years ago
• SymbioticEDA / getting-started-FV
  ☆18Updated 5 years ago
• isec-tugraz / coco-alma
  CocoAlma is an execution-aware tool for formal verification of masked implementations
  ☆24Updated last year
• EDAPack / edapack
  Provides a packaged collection of open source EDA tools
  ☆12Updated 6 years ago
• laurentc2 / ASAP7_for_KLayout
  KLayout technology files for ASAP7 FinFET educational process
  ☆24Updated 3 years ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆51Updated 10 years ago
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆18Updated 9 months ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆56Updated 3 years ago
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆17Updated 4 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆44Updated 2 years ago
• snishizawa / asap7_snps
  Supplemental technology files for ASAP7 PDK with Synopsys design flow
  ☆22Updated 3 years ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆28Updated 3 years ago
• lip6 / coriolis
  Coriolis VLSI EDA Tool (LIP6)
  ☆77Updated 2 weeks ago
• Nic30 / hwtHls
  LLVM based HLS library for HWToolkit (hardware devel. toolkit)
  ☆27Updated 2 weeks ago
• HardwareIR / netlistDB
  netlistDB - Intermediate format for digital hardware representation with graph database API
  ☆31Updated 4 years ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆35Updated 5 years ago
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆19Updated 3 years ago
• mit-ll / CEP
  The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…
  ☆68Updated 3 years ago
• aolofsson / POSH
  ☆44Updated 6 years ago
• verilog-to-routing / libblifparse
  Parsing library for BLIF netlists
  ☆19Updated last year
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆52Updated 9 months ago
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year
• pulp-platform / ELAU
  ☆20Updated last year
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated 3 weeks ago
• sterin / super-prove-build
  ☆14Updated 5 years ago
• b224hisl / rioschip
  ☆33Updated 3 years ago
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆35Updated 2 months ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆62Updated last week
• jinwookjungs / open_design_flow
  OpenDesign Flow Database
  ☆17Updated 7 years ago