xprova / netlist-graphLinks
Java library for parsing and manipulating graph representations of gate-level Verilog netlists
☆14Updated 8 years ago
Alternatives and similar repositories for netlist-graph
Users that are interested in netlist-graph are comparing it to the libraries listed below
Sorting:
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- A library and command-line tool for querying a Verilog netlist.☆28Updated 3 years ago
- netlistDB - Intermediate format for digital hardware representation with graph database API☆31Updated 4 years ago
- The PE for the second generation CGRA (garnet).☆17Updated 4 months ago
- Collection of test cases for Yosys☆18Updated 3 years ago
- An open source PDK using TIGFET 10nm devices.☆51Updated 2 years ago
- LLVM based HLS library for HWToolkit (hardware devel. toolkit)☆25Updated 2 months ago
- ☆19Updated last year
- Implementation of the Advanced Encryption Standard in Chisel☆19Updated 3 years ago
- ☆18Updated 5 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- A fault-injection framework using Chisel and FIRRTL☆37Updated this week
- YosysHQ SVA AXI Properties☆42Updated 2 years ago
- CMake based hardware build system☆31Updated last week
- Intel Compiler for SystemC☆24Updated 2 years ago
- Provides a packaged collection of open source EDA tools☆12Updated 6 years ago
- A Python package for testing hardware (part of the magma ecosystem)☆45Updated last year
- ☆33Updated 2 years ago
- ☆44Updated 5 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆50Updated 9 years ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆65Updated 2 years ago
- Parsing library for BLIF netlists☆19Updated 10 months ago
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- ☆56Updated 3 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆38Updated 2 months ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- mantle library☆44Updated 2 years ago
- Determines the modules declared and instantiated in a SystemVerilog file☆47Updated 11 months ago
- Supplemental technology files for ASAP7 PDK with Synopsys design flow☆17Updated 2 years ago
- ☆31Updated last year