xprova / netlist-graph
Java library for parsing and manipulating graph representations of gate-level Verilog netlists
☆13Updated 7 years ago
Related projects ⓘ
Alternatives and complementary repositories for netlist-graph
- netlistDB - Intermediate format for digital hardware representation with graph database API☆29Updated 3 years ago
- Collection of test cases for Yosys☆16Updated 2 years ago
- Provides a packaged collection of open source EDA tools☆12Updated 5 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆26Updated 3 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆20Updated last week
- OpenDesign Flow Database☆16Updated 6 years ago
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- LibreSilicon's Standard Cell Library Generator☆17Updated 6 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆39Updated last year
- Mirror of tachyon-da cvc Verilog simulator☆37Updated last year
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆28Updated 3 months ago
- Implementation of the Advanced Encryption Standard in Chisel☆19Updated 2 years ago
- The ANUBIS benchmark suite for Incremental Synthesis☆12Updated 3 years ago
- The PE for the second generation CGRA (garnet).☆16Updated 2 months ago
- Cross EDA Abstraction and Automation☆35Updated 2 weeks ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆31Updated 2 weeks ago
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆21Updated 4 years ago
- IP-core package generator for AXI4/Avalon☆21Updated 5 years ago
- Hardware Formal Verification☆15Updated 4 years ago
- Handle Fast Signal Traces (fst) in Python☆10Updated 2 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- Magic VLSI Layout Tool☆19Updated 5 years ago
- sram/rram/mram.. compiler☆28Updated last year
- SCARV: a side-channel hardened RISC-V platform☆24Updated last year
- Benchmarks for Yosys development☆21Updated 4 years ago
- A basic documentation generator for Verilog, similar to Doxygen.☆11Updated 8 years ago
- ☆18Updated 4 years ago
- Parsing library for BLIF netlists☆18Updated last week
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆14Updated 4 years ago