This is a probabilistic SAT attack tool.
☆13Jun 5, 2021Updated 4 years ago
Alternatives and similar repositories for PSAT
Users that are interested in PSAT are comparing it to the libraries listed below
Sorting:
- A basic implementation of a SAT attack on logic locking.☆13Jun 30, 2021Updated 4 years ago
- SMT Attack☆22Mar 5, 2021Updated 4 years ago
- ☆23Mar 13, 2023Updated 2 years ago
- Lock circuitgraphs using various logic locking techniques☆11May 2, 2023Updated 2 years ago
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆15Jan 9, 2017Updated 9 years ago
- Lingeling SAT Solver☆105Mar 12, 2024Updated last year
- Hardware Security Labs☆31May 3, 2017Updated 8 years ago
- WebRTCを使ってブラウザ間通信を行うオンセツール ユドナリウムの変更版ユドナリウムリリィです☆18Jan 22, 2026Updated last month
- Used for hardware trojan detection（Based on Trust_Hub）☆10Jul 30, 2019Updated 6 years ago
- ☆14Oct 29, 2023Updated 2 years ago
- ☆11Nov 10, 2025Updated 3 months ago
- ☆16Nov 8, 2024Updated last year
- CrazyDiskInfo is an interactive TUI S.M.A.R.T viewer for Unix systems.☆10Aug 9, 2022Updated 3 years ago
- HELM: Navigating Homomorphic Encryption through Gates and Lookup Tables☆11Apr 7, 2025Updated 10 months ago
- A copy of the latest version of MVSIS☆12Apr 18, 2021Updated 4 years ago
- Proof-of-concept implementation for the paper "Homomorphic Encryption for Large Integers from Nested Residue Number Systems", presented a…☆27Jun 4, 2025Updated 9 months ago
- BuDDy BDD package (with CMake support)☆15May 7, 2024Updated last year
- A WIP library to control B1500 and similar testers via the VISA protocol, built on pyvisa☆11Nov 4, 2016Updated 9 years ago
- Framework based on Partial Reconfiguration for chip characterization utilizing ring-oscillator PUFs☆13Apr 1, 2020Updated 5 years ago
- Synthesiser for Asynchronous Verilog Language☆20Oct 29, 2014Updated 11 years ago
- [TVLSI 2025] ACiM Inference Simulation Framework in "ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits"☆27Sep 9, 2025Updated 5 months ago
- A library to parse BLIF (Berkeley Logic Interchange Format) files.☆10Mar 11, 2015Updated 10 years ago
- 2-core MIPS R10K OoO Processor with Snooping MSI and Pipeline Bus☆11Jan 5, 2018Updated 8 years ago
- A library for lattice-based homomorphic encryption in Go☆14May 15, 2022Updated 3 years ago
- ☆12Apr 6, 2025Updated 10 months ago
- Quantized training method for RRAM-based systems.☆12Sep 24, 2018Updated 7 years ago
- RTL code for the DPU chip designed for irregular graphs☆13May 30, 2022Updated 3 years ago
- 基于tenserflow2.10与yolo v4开发的目标检测、测距、避障提示☆14Dec 23, 2023Updated 2 years ago
- SDR-Transceiver☆10Dec 30, 2019Updated 6 years ago
- Stencila for Python☆17Aug 3, 2018Updated 7 years ago
- A Rust Hardware Abstraction Layer for the MAX78000 microcontroller☆13Feb 27, 2025Updated last year
- ☆10Apr 13, 2020Updated 5 years ago
- Skeleton (but pronounced like Peloton): A Zero-Click RCE exploit for CVE-2021-0326☆20Mar 16, 2022Updated 3 years ago
- Tool for parsing an integrated circuit test file from STIL to the particular file format of a Teradyne tester.☆15May 17, 2018Updated 7 years ago
- ☆10Apr 30, 2018Updated 7 years ago
- Experimental port of the TFHE fully homomorphic encryption scheme to Rust.☆12Aug 15, 2022Updated 3 years ago
- A modular library for designing and optimising homomorphic encryption schemes☆25Feb 24, 2026Updated last week
- Chisel Fixed-Point Arithmetic Library☆18Dec 15, 2025Updated 2 months ago
- Dynex has also developed a proprietary circuit design, the Dynex Neuromorphic Chip, that complements the Dynex ecosystem and turns any mo…☆15May 26, 2023Updated 2 years ago