Alternatives and similar repositories for PSAT

Users that are interested in PSAT are comparing it to the libraries listed below

• lnestor / sat_attack
  A basic implementation of a SAT attack on logic locking.
  ☆12Updated 3 years ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆83Updated last year
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆27Updated 5 years ago
• spider-tronix / Standard-Cell-Characterization
  Open Source tool to build liberty files and for Characterizing Standard Cells.
  ☆27Updated 4 years ago
• circuitgraph / logiclocking
  Lock circuitgraphs using various logic locking techniques
  ☆10Updated 2 years ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆59Updated last month
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆49Updated 5 months ago
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆33Updated 3 weeks ago
• ehw-fit / ariths-gen
  Generator of arithmetic circuits (multipliers, adders) and approximate circuits
  ☆35Updated 4 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆42Updated 2 years ago
• Centre-for-Hardware-Security / asap7_reference_design
  reference block design for the ASAP7nm library in Cadence Innovus
  ☆44Updated last year
• bluesceada / iscas89_hl_verilog
  Re-host of ISCAS89 sequential benchmark circuits in higher level verilog (without "DFF")
  ☆14Updated 3 years ago
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆20Updated 3 years ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆45Updated 2 weeks ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆52Updated 5 years ago
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆18Updated last month
• Ghonimo / Formal-Verification-With-VC-Formal--Tutorials-and-Examples
  This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…
  ☆31Updated last year
• gatelabdavis / SMTAttack
  SMT Attack
  ☆21Updated 4 years ago
• csail-csg / pyverilator
  Python wrapper for verilator model
  ☆86Updated last year
• marlls1989 / ascend-freepdk45
  A free standard cell library for SDDS-NCL circuits
  ☆27Updated 2 years ago
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆48Updated 4 years ago
• pulp-platform / svase
  ☆32Updated 5 months ago
• cornell-brg / pymtl3-net
  Project repo for the POSH on-chip network generator
  ☆46Updated 3 months ago
• yaozhaosh / chisel-aes
  Chisel implementation of AES
  ☆23Updated 5 years ago
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆37Updated 2 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆57Updated last week
• fukatani / Pyverilog_toolbox
  ☆40Updated 7 years ago
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆70Updated 4 years ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆51Updated last week
• AmeerAbdelhadi / Multiported-RAM
  Modular Multi-ported SRAM-based Memory
  ☆30Updated 7 months ago