Alternatives and similar repositories for PSAT

Users that are interested in PSAT are comparing it to the libraries listed below

• lnestor / sat_attack
  A basic implementation of a SAT attack on logic locking.
  ☆13Updated 4 years ago
• circuitgraph / logiclocking
  Lock circuitgraphs using various logic locking techniques
  ☆10Updated 2 years ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆98Updated last year
• The-OpenROAD-Project / asap7
  ☆232Updated 10 months ago
• ehw-fit / ariths-gen
  Generator of arithmetic circuits (multipliers, adders) and approximate circuits
  ☆39Updated 5 months ago
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆29Updated 6 years ago
• ucb-bar / sha3
  ☆82Updated last year
• NTU-LaDS-II / FAN_ATPG
  FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
  ☆106Updated 6 months ago
• hsluoyz / Atalanta
  Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.
  ☆87Updated last year
• nbulsi / also
  A logic synthesis tool
  ☆85Updated 4 months ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆163Updated 2 months ago
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆178Updated 5 months ago
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆279Updated last month
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆226Updated 10 months ago
• csail-csg / pyverilator
  Python wrapper for verilator model
  ☆92Updated last year
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆160Updated last year
• spider-tronix / Standard-Cell-Characterization
  Open Source tool to build liberty files and for Characterizing Standard Cells.
  ☆28Updated 4 years ago
• Ghonimo / Formal-Verification-With-VC-Formal--Tutorials-and-Examples
  This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…
  ☆45Updated last year
• ncsu-eda / FreePDK3
  ☆187Updated 4 years ago
• aneeshkandi14 / ascon-hw-public
  ☆22Updated last year
• UCLA-VAST / RapidStream
  [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
  ☆128Updated 3 years ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆194Updated this week
• cad-polito-it / I99T
  ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino
  ☆67Updated 8 months ago
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆355Updated last week
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆127Updated last year
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆214Updated last week
• isec-tugraz / coco-alma
  CocoAlma is an execution-aware tool for formal verification of masked implementations
  ☆24Updated last year
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆118Updated last week
• eriksargent / PUF-lab
  FPGA implementation of a physical unclonable function for authentication
  ☆33Updated 8 years ago
• gpt4rtl / AutoSVA2
  ☆17Updated 2 years ago