Alternatives and similar repositories for PSAT

Users that are interested in PSAT are comparing it to the libraries listed below

• lnestor / sat_attack
  A basic implementation of a SAT attack on logic locking.
  ☆13Updated 4 years ago
• aneeshkandi14 / ascon-hw-public
  ☆21Updated last year
• ehw-fit / ariths-gen
  Generator of arithmetic circuits (multipliers, adders) and approximate circuits
  ☆39Updated 4 months ago
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆29Updated 5 years ago
• The-OpenROAD-Project / asap7
  ☆223Updated 9 months ago
• circuitgraph / logiclocking
  Lock circuitgraphs using various logic locking techniques
  ☆10Updated 2 years ago
• hsluoyz / Atalanta
  Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.
  ☆85Updated last year
• NTU-LaDS-II / FAN_ATPG
  FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
  ☆103Updated 6 months ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆96Updated last year
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆223Updated 9 months ago
• spider-tronix / Standard-Cell-Characterization
  Open Source tool to build liberty files and for Characterizing Standard Cells.
  ☆28Updated 4 years ago
• mflowgen / freepdk-45nm
  ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
  ☆196Updated 5 years ago
• nbulsi / also
  A logic synthesis tool
  ☆84Updated 3 months ago
• circuitgraph / circuitgraph
  Tools for working with circuits as graphs in python
  ☆127Updated 2 years ago
• lnis-uofu / LSOracle
  IDEA project source files
  ☆111Updated 2 months ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆159Updated last year
• UCLA-VAST / RapidStream
  [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
  ☆127Updated 3 years ago
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆275Updated 3 weeks ago
• OpenTimer / Parser-Verilog
  A Standalone Structural Verilog Parser
  ☆99Updated 3 years ago
• ucb-bar / sha3
  ☆82Updated last year
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆60Updated 11 months ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆162Updated last month
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆174Updated 4 months ago
• mit-ll / CEP
  The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…
  ☆67Updated 3 years ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆75Updated last month
• ncsu-eda / FreePDK3
  ☆183Updated 4 years ago
• cornell-brg / pymtl3-net
  Project repo for the POSH on-chip network generator
  ☆52Updated 9 months ago
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆118Updated last week
• Ghonimo / Formal-Verification-With-VC-Formal--Tutorials-and-Examples
  This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…
  ☆43Updated last year
• mongrelgem / Verilog-Adders
  Implementing Different Adder Structures in Verilog
  ☆76Updated 6 years ago