Alternatives and similar repositories for PSAT:

Users that are interested in PSAT are comparing it to the libraries listed below

• lnestor / sat_attack
  A basic implementation of a SAT attack on logic locking.
  ☆12Updated 3 years ago
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆24Updated 5 years ago
• ehw-fit / ariths-gen
  Generator of arithmetic circuits (multipliers, adders) and approximate circuits
  ☆30Updated this week
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆75Updated 10 months ago
• yzwangfeng / reram-synthesis
  A synthesis flow for hybrid processing-in-RRAM modes
  ☆12Updated 3 years ago
• aneeshkandi14 / ascon-hw-public
  ☆18Updated 6 months ago
• spider-tronix / Standard-Cell-Characterization
  Open Source tool to build liberty files and for Characterizing Standard Cells.
  ☆24Updated 3 years ago
• NTU-LaDS-II / FAN_ATPG
  FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
  ☆81Updated last year
• hsluoyz / Atalanta
  Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.
  ☆77Updated 8 months ago
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆20Updated 2 years ago
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆79Updated 2 months ago
• jinwookjungs / open_design_flow
  OpenDesign Flow Database
  ☆16Updated 6 years ago
• Centre-for-Hardware-Security / asap7_reference_design
  reference block design for the ASAP7nm library in Cadence Innovus
  ☆33Updated 7 months ago
• rahulk29 / sram22_sky130_macros
  SKY130 SRAM macros generated by SRAM 22
  ☆11Updated last week
• habibagamal / SoC_Automation
  SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …
  ☆37Updated 4 years ago
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆64Updated 3 years ago
• cad-polito-it / I99T
  ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino
  ☆49Updated last year
• oprecomp / DDR4_controller
  ☆50Updated 3 years ago
• kunalg123 / icc2_workshop_collaterals
  This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…
  ☆30Updated 4 years ago
• mongrelgem / Verilog-Adders
  Implementing Different Adder Structures in Verilog
  ☆60Updated 5 years ago
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆59Updated 5 years ago
• scale-lab / DRUM
  The Verilog source code for DRUM approximate multiplier.
  ☆29Updated last year
• aolofsson / POSH
  ☆40Updated 5 years ago
• pulp-platform / svase
  ☆31Updated 3 weeks ago
• fatestudio / RSA4096_NEW
  ☆12Updated 9 years ago
• yellekelyk / PyVerilog
  Python-based Verilog Parser (currently Netlist only)
  ☆53Updated 7 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆61Updated last month
• IObundle / iob-versat
  Coarse Grained Reconfigurable Array
  ☆19Updated 6 months ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆46Updated this week
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆156Updated this week