abdelazeem201 / ICC2_scriptsLinks
This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.
☆18Updated last year
Alternatives and similar repositories for ICC2_scripts
Users that are interested in ICC2_scripts are comparing it to the libraries listed below
Sorting:
- AXI DMA 32 / 64 bits☆115Updated 10 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- VIP for AXI Protocol☆139Updated 3 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Updated 4 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆19Updated last year
- An AXI4 crossbar implementation in SystemVerilog☆161Updated 3 weeks ago
- AXI总线连接器☆100Updated 5 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆126Updated 7 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆87Updated 6 years ago
- A verilog implementation for Network-on-Chip☆74Updated 7 years ago
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- PCIE 5.0 Graduation project (Verification Team)☆78Updated last year
- yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/☆121Updated 7 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆12Updated 4 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆127Updated 4 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆63Updated last year
- AMBA bus generator including AXI, AHB, and APB☆105Updated 3 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆62Updated 2 years ago
- Some useful documents of Synopsys☆75Updated 3 years ago
- ☆46Updated 4 years ago
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆105Updated 6 months ago
- UVM AHB VIP☆86Updated 7 months ago
- SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core☆144Updated 7 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆78Updated 7 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆92Updated 2 years ago
- UVM examples and projects☆140Updated 2 weeks ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆208Updated 2 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆65Updated 11 months ago
- AXI Interconnect☆50Updated 3 years ago
- ☆34Updated 6 years ago