abdelazeem201 / ICC2_scriptsLinks
This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.
☆20Updated last year
Alternatives and similar repositories for ICC2_scripts
Users that are interested in ICC2_scripts are comparing it to the libraries listed below
Sorting:
- VIP for AXI Protocol☆148Updated 3 years ago
- AXI DMA 32 / 64 bits☆121Updated 11 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆129Updated 7 years ago
- An AXI4 crossbar implementation in SystemVerilog☆170Updated this week
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆64Updated 2 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆20Updated last year
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Updated 4 years ago
- Some useful documents of Synopsys☆82Updated 3 years ago
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆130Updated 4 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆75Updated last year
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆31Updated last year
- AMBA bus generator including AXI, AHB, and APB☆106Updated 4 years ago
- yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/☆124Updated 7 years ago
- Network on Chip Implementation written in SytemVerilog☆189Updated 3 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆65Updated last year
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆90Updated 6 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆79Updated 7 years ago
- ☆47Updated 4 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆96Updated 2 years ago
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆106Updated 8 months ago
- AXI总线连接器☆103Updated 5 years ago
- ☆13Updated 2 years ago
- SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core☆147Updated 7 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆37Updated 5 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆39Updated 3 years ago
- AMBA AHB 2.0 VIP in SystemVerilog UVM☆152Updated 5 years ago
- A verilog implementation for Network-on-Chip☆76Updated 7 years ago
- This is the main repository for all the examples for the book Practical UVM☆201Updated 4 years ago
- UVM examples and projects☆142Updated 2 months ago