Yujie-Cui / WB-channelsLinks
☆13Updated 3 years ago
Alternatives and similar repositories for WB-channels
Users that are interested in WB-channels are comparing it to the libraries listed below
Sorting:
- Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.☆60Updated 5 years ago
- The artifact for SecSMT paper -- Usenix Security 2022☆27Updated 3 years ago
- CleanupSpec (MICRO-2019)☆16Updated 4 years ago
- Data-centric defense mechanism against Spectre attacks. (DAC'19)☆11Updated 5 years ago
- New Cache implementation using Gem5☆13Updated 11 years ago
- Streamline Covert Channel Attack (presented in ASPLOS'21)☆20Updated 4 years ago
- ☆35Updated 4 years ago
- ☆19Updated 3 years ago
- ☆25Updated 2 years ago
- A behavioural cache model for analysing the cache behaviour under side-channel attack.☆26Updated 3 months ago
- ☆33Updated 5 years ago
- MESIF cache coherency protocol for the GEM5 simulator☆15Updated 9 years ago
- ☆17Updated 4 years ago
- The official repository for the gem5 resources sources.☆73Updated 2 months ago
- Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly☆17Updated 4 years ago
- ☆12Updated 6 years ago
- Hands on with side-channels: a tutorial on covert-channels built using shared CPU resources. Three different covert-channel implementatio…☆50Updated 6 years ago
- MIRAGE (USENIX Security 2021)☆13Updated last year
- An artifact for Berti: an Accurate and Timely Local-Delta Data Prefetcher☆32Updated 2 years ago
- Artifact, reproducibility, and testing utilites for gem5☆23Updated 4 years ago
- Joint HPS and ETH Repository to work towards open sourcing Scarab and Ramulator☆80Updated 3 weeks ago
- Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)☆65Updated 5 years ago
- This repository provides Pensieve, a security evaluation framework for microarchitectural defenses against speculative execution attacks.☆23Updated last year
- Library for Prime+Probe cache side-channel attacks on L1 and L2☆36Updated 5 years ago
- ☆13Updated 4 years ago
- NVLeak: Off-Chip Side-Channel Attacks via Non-Volatile Memory Systems [USENIX Security '23]☆18Updated 2 years ago
- SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. T…☆138Updated 2 years ago
- This repository is meant to be a guide for building your own prefetcher for CPU caches and evaluating it, using ChampSim simulator☆41Updated 3 years ago
- Gem5 with chinese comment and introduction (master) and some other std gem5 version.☆42Updated 3 years ago
- Security Test Benchmark for Computer Architectures☆21Updated last week