Alternatives and similar repositories for WB-channels

Users that are interested in WB-channels are comparing it to the libraries listed below

• PittECEArch / AdversarialPrefetch
  ☆19Updated 2 years ago
• gururaj-s / cleanupspec
  CleanupSpec (MICRO-2019)
  ☆17Updated 4 years ago
• mjyan0720 / InvisiSpec-1.0
  Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.
  ☆60Updated 5 years ago
• mktrm / SecSMT_Artifact
  The artifact for SecSMT paper -- Usenix Security 2022
  ☆27Updated 2 years ago
• cwfletcher / stt
  ☆35Updated 4 years ago
• CSL-KU / SpectreGuard
  Data-centric defense mechanism against Spectre attacks. (DAC'19)
  ☆11Updated 5 years ago
• fanyao / branchspec
  Proof of concept code for the BranchSpec exploit.
  ☆9Updated 2 years ago
• eepalms / gem5-newcache
  New Cache implementation using Gem5
  ☆13Updated 11 years ago
• gururaj-s / streamline
  Streamline Covert Channel Attack (presented in ASPLOS'21)
  ☆20Updated 4 years ago
• comparch-security / cache-model
  A behavioural cache model for analysing the cache behaviour under side-channel attack.
  ☆25Updated 8 months ago
• compsec-snu / specdoctor
  ☆25Updated 2 years ago
• UT-LCA / Scalability-Phase-Simpoint-of-SPEC-CPU2017
  ☆32Updated 5 years ago
• darchr / gem5art-experiments
  Experiments for gem5art paper
  ☆9Updated 3 years ago
• gururaj-s / mirage
  MIRAGE (USENIX Security 2021)
  ☆13Updated last year
• MATCHA-MIT / Pensieve
  This repository provides Pensieve, a security evaluation framework for microarchitectural defenses against speculative execution attacks.
  ☆23Updated last year
• 0x161e-swei / covert-channel-101
  ☆12Updated 5 years ago
• CTSRD-CHERI / Test-Suite-Transient-Execution
  Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly
  ☆15Updated 3 years ago
• agusnt / Berti-Artifact
  An artifact for Berti: an Accurate and Timely Local-Delta Data Prefetcher
  ☆30Updated 2 years ago
• greenlsi / reload_refresh
  Reload+Refresh PoC
  ☆14Updated 5 years ago
• qiyancos / gem5-with-chinese-comment
  Gem5 with chinese comment and introduction (master) and some other std gem5 version.
  ☆42Updated 3 years ago
• jkadlec / gem5-l3-mesif
  MESIF cache coherency protocol for the GEM5 simulator
  ☆14Updated 9 years ago
• darchr / parsec-benchmark
  ☆17Updated 4 years ago
• ECLab-ITU / Cache-Side-Channel-Attacks
  This repository contains source code and experimental data of multiple cache side-channel attacks on Intel x86 architecture.
  ☆52Updated 5 years ago
• yshalabi / covert-channel-tutorial
  Hands on with side-channels: a tutorial on covert-channels built using shared CPU resources. Three different covert-channel implementatio…
  ☆48Updated 5 years ago
• efeslab / dolma
  ☆12Updated 4 years ago
• zzrcxb / PinnedLoads
  Gem5 implementation of Pinned Loads: Taming Speculative Loads in Secure Processors
  ☆9Updated 2 years ago
• Miro-H / CacheSC
  Library for Prime+Probe cache side-channel attacks on L1 and L2
  ☆34Updated 4 years ago
• darchr / gem5art
  Artifact, reproducibility, and testing utilites for gem5
  ☆22Updated 3 years ago
• darchr / Keystone-experiments
  ☆11Updated 3 years ago
• comparch-security / cpu-sec-bench
  Security Test Benchmark for Computer Architectures
  ☆21Updated 3 months ago