Yujie-Cui / WB-channelsView external linksLinks
☆13May 26, 2022Updated 3 years ago
Alternatives and similar repositories for WB-channels
Users that are interested in WB-channels are comparing it to the libraries listed below
Sorting:
- Streamline Covert Channel Attack (presented in ASPLOS'21)☆22Feb 18, 2021Updated 4 years ago
- HW interface for memory caches☆28Apr 21, 2020Updated 5 years ago
- This repository contains source code and experimental data of multiple cache side-channel attacks on Intel x86 architecture.☆57Aug 21, 2019Updated 6 years ago
- ☆16Mar 18, 2025Updated 10 months ago
- The open-source component of Prime+Scope, published at CCS 2021☆37Jul 18, 2023Updated 2 years ago
- CleanupSpec (MICRO-2019)☆16Oct 22, 2020Updated 5 years ago
- Reload+Refresh PoC☆16Feb 26, 2020Updated 5 years ago
- Research code to perform AES timing attacks circa 2006☆15Feb 13, 2014Updated 12 years ago
- ☆21Jun 17, 2022Updated 3 years ago
- AutoCAT: Reinforcement Learning for Automated Exploration of Cache-Timing Attacks☆46May 19, 2023Updated 2 years ago
- ☆20Aug 3, 2018Updated 7 years ago
- CodeWithMosh_Sql_LearningNotes☆16Feb 21, 2022Updated 3 years ago
- Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.☆61Apr 27, 2020Updated 5 years ago
- A flush-reload side channel attack implementation☆56Mar 26, 2022Updated 3 years ago
- Tool for testing and finding minimal eviction sets☆107May 6, 2021Updated 4 years ago
- ☆197Jun 12, 2024Updated last year
- [UNMAINTAINED] Implementation of the FLUSH+RELOAD side channel attack☆63Nov 4, 2017Updated 8 years ago
- An artifact for Berti: an Accurate and Timely Local-Delta Data Prefetcher☆36Nov 9, 2022Updated 3 years ago
- Repository code to support paper TCHES2020 paper "Remove Some Noise: On Pre-processing of Side-channel Measurements with Autoencoders"☆13Jun 4, 2022Updated 3 years ago
- Releasing open-sourced version of the code used in the paper "Perceptron-based Prefetch Filtering (ISCA 2019)"☆10May 27, 2022Updated 3 years ago
- Slice-aware Memory Management - Exploiting NUCA Characteristic of LLC in Intel Processors☆41May 20, 2019Updated 6 years ago
- ☆13Jul 19, 2024Updated last year
- This is a GIT syncronization of https://wiki.newae.com☆10Feb 21, 2018Updated 7 years ago
- Example of Chisel3 Diplomacy☆11Feb 23, 2022Updated 3 years ago
- Iodine: Verifying Constant-Time Execution of Hardware☆15Mar 29, 2021Updated 4 years ago
- Optimization for Onmyoji☆14Apr 25, 2020Updated 5 years ago
- ☆12Sep 18, 2024Updated last year
- ☆11Mar 17, 2021Updated 4 years ago
- A High-Performance Side-Channel-Resistant AES on GPUs☆13May 9, 2019Updated 6 years ago
- Running ahead of memory latency - Part II project☆10Jan 7, 2023Updated 3 years ago
- ☆12Jun 22, 2021Updated 4 years ago
- An Easy to Use C++ Header-only Log Project, C++11 is not necessary☆12Jan 5, 2019Updated 7 years ago
- ☆12Aug 8, 2024Updated last year
- Some demo for template side channel attacks☆13Dec 18, 2020Updated 5 years ago
- DeepGate3 for ICCAD2024☆13May 26, 2025Updated 8 months ago
- EstraNet: An Efficient Shift-Invariant Transformer Network for Side Channel Analysis☆11Aug 26, 2025Updated 5 months ago
- HLS project modeling various sparse accelerators.☆12Jan 11, 2022Updated 4 years ago
- Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.☆18Feb 3, 2026Updated last week
- Forge PKCS1v1.5 signature for questionable implementation of verification algorithms...☆10Jun 26, 2024Updated last year