cucapra / patronusLinks
work in progress, playing around with btor2 in rust
☆11Updated this week
Alternatives and similar repositories for patronus
Users that are interested in patronus are comparing it to the libraries listed below
Sorting:
- BTOR2 MLIR project☆26Updated last year
- easter egg is a flexible, high-performance e-graph library with support of multiple additional assumptions at once☆13Updated 7 months ago
- PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…☆22Updated 4 months ago
- Bᴛᴏʀ2MLIR: A Format and Toolchain for Hardware Verification☆20Updated last month
- The source code to the Voss II Hardware Verification Suite☆56Updated last month
- ☆19Updated last year
- A formally verified high-level synthesis tool based on CompCert and written in Coq.☆94Updated last month
- Using e-graphs to synthesize netlists from boolean logic.☆14Updated 2 years ago
- Control Logic Synthesis: Drawing the Rest of the OWL☆13Updated last year
- rIC3 model checker for Hardware Model Checking Competition 2024(HWMCC'24) submission☆12Updated 3 months ago
- Verilog development and verification project for HOL4☆27Updated 6 months ago
- CoreIR Symbolic Analyzer☆74Updated 5 years ago
- ☆13Updated 4 years ago
- Tools for manipulating CHC and related files☆15Updated 2 years ago
- Random Generator of Btor2 Files☆10Updated 2 years ago
- A Hardware Pipeline Description Language☆48Updated 3 months ago
- Automatically generate a compiler using equality saturation☆34Updated last year
- E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis (DAC2025)☆22Updated 4 months ago
- Verilog AST☆21Updated last year
- FPGA synthesis tool powered by program synthesis☆51Updated 3 weeks ago
- Collection of utlities for writing parsers. Includes a fast DIMACS CNF parser.☆15Updated 11 months ago
- Create auto-scheduled data-parallel pipelines in hardware with user-friendly Python☆13Updated 4 years ago
- ☆14Updated 7 years ago
- CHERI-RISC-V model written in Sail☆65Updated 3 months ago
- ☆10Updated 4 years ago
- Iodine: Verifying Constant-Time Execution of Hardware☆14Updated 4 years ago
- ☆40Updated 4 years ago
- Testing processors with Random Instruction Generation☆47Updated 2 weeks ago
- Refreshing automation for inductive equational proofs using e-graphs☆24Updated last year
- A Coq framework to support structural design and proof of hardware cache-coherence protocols☆14Updated 3 years ago