mit-ll / CEP
The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.
☆60Updated last year
Related projects: ⓘ
- ☆65Updated last year
- pulp_soc is the core building component of PULP based SoCs☆76Updated last month
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆80Updated 3 years ago
- ☆66Updated this week
- AXI Adapter(s) for RISC-V Atomic Operations☆58Updated 3 weeks ago
- CVA6 SDK containing RISC-V tools and Buildroot☆59Updated 2 months ago
- ☆68Updated last year
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 2 years ago
- FPGA reference design for the the Swerv EH1 Core☆65Updated 4 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆72Updated 5 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 3 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆66Updated 4 months ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 4 years ago
- ☆76Updated 6 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆45Updated 4 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆44Updated 8 years ago
- Verilog Content Addressable Memory Module☆100Updated 2 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆72Updated 5 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆47Updated 8 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆57Updated 5 months ago
- A SystemVerilog source file pickler.☆49Updated 9 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆56Updated 3 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆94Updated 3 years ago
- Tests for example Rocket Custom Coprocessors☆68Updated 4 years ago
- Builds, flow and designs for the alpha release☆53Updated 4 years ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆118Updated 6 months ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆74Updated 3 weeks ago
- HW Design Collateral for Caliptra RoT IP☆65Updated this week
- ☆51Updated 2 years ago
- DEPRECATED. Please use Chipyard (https://github.com/ucb-bar/chipyard) to build BOOM☆35Updated 4 years ago