mit-ll / CEPLinks
The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.
☆67Updated 3 years ago
Alternatives and similar repositories for CEP
Users that are interested in CEP are comparing it to the libraries listed below
Sorting:
- pulp_soc is the core building component of PULP based SoCs☆82Updated 10 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆88Updated 4 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆80Updated last year
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 4 years ago
- ☆68Updated 3 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆98Updated last year
- Advanced Interface Bus (AIB) die-to-die hardware open source☆146Updated last year
- A SystemVerilog source file pickler.☆60Updated last year
- ☆58Updated 10 months ago
- A collection of big designs to run post-synthesis simulations with yosys☆51Updated 10 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 7 months ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆88Updated last year
- ☆113Updated 2 months ago
- FPGA reference design for the the Swerv EH1 Core☆72Updated 6 years ago
- (System)Verilog to Chisel translator☆116Updated 3 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆98Updated last month
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 3 months ago
- ☆82Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆69Updated 11 months ago
- OmniXtend cache coherence protocol☆82Updated 7 months ago
- RISC-V Verification Interface☆135Updated last week
- Basic floating-point components for RISC-V processors☆67Updated 6 years ago
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆153Updated 3 weeks ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- The multi-core cluster of a PULP system.☆111Updated last month
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- ☆44Updated 6 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆50Updated 9 years ago