Alternatives and similar repositories for SoC_Vulnerability_Benchmarks

Users that are interested in SoC_Vulnerability_Benchmarks are comparing it to the libraries listed below

• ZSusskind / vcd2csv
  Extracts specified data from a VCD file into CSV form
  ☆10Updated 6 years ago
• opentrng / ptrng
  Open-source implementations of reference Physical True Random Number Generators (TRNG or PTRNG) based on ring oscillators.
  ☆13Updated 3 months ago
• zero-day-labs / riscv-iopmp
  IOPMP IP
  ☆21Updated 6 months ago
• antmicro / rowhammer-tester
  ☆72Updated last month
• proteus-core / proteus
  The SpinalHDL design of the Proteus core, an extensible RISC-V core.
  ☆59Updated last week
• lowRISC / ot-sca
  Side-channel analysis setup for OpenTitan
  ☆37Updated 2 months ago
• agra-uni-bremen / symex-vp
  A concolic testing engine for RISC-V embedded software with support for SystemC peripherals
  ☆27Updated 2 years ago
• openhwgroup / cvw-arch-verif
  The purpose of the repo is to support CORE-V Wally architectural verification
  ☆16Updated 2 months ago
• zero-day-labs / riscv-iommu-demo
  RISC-V IOMMU Demo (Linux & Bao)
  ☆23Updated 2 years ago
• CommonEvaluationPlatform / CEP
  The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely…
  ☆26Updated last year
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆124Updated last week
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆98Updated last year
• Chair-for-Security-Engineering / AES_masked_BRAM
  Designs of first-order SCA-secure hardware implementations of AES encryption/decryptoin dedicated to Xilinx FPGAs (using BRAM)
  ☆16Updated 5 years ago
• Learning-Chips-Lab / OpenEye
  The Open Source Hardware Accelerator for Efficient Neural Network Inference
  ☆48Updated last week
• newaetech / CW305-Arm-DesignStart
  Instruction and files for porting Arm DesignStart to CW305.
  ☆16Updated 2 years ago
• openhwgroup / cva6-platform
  CVA6-platform is a multicore CVA6 with CV-MESH software and regression platform
  ☆12Updated 2 years ago
• comsec-group / encarsia
  ☆26Updated 9 months ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆76Updated last month
• openhwgroup / core-v-polara-apu
  The OpenPiton Platform
  ☆17Updated last year
• isec-tugraz / coco-alma
  CocoAlma is an execution-aware tool for formal verification of masked implementations
  ☆23Updated last year
• ESCristiano / BUSted
  BUSted!!! Microarchitectural Side-Channel Attacks on the MCU Bus Interconnect
  ☆11Updated last year
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆72Updated 2 years ago
• chili-chips-ba / openPCIE
  Peripheral Component Interconnect (PCI) has taken the Express lane long ago, moving to xGbps SerDes. Now for the first time in opensource…
  ☆53Updated this week
• scarv / scarv
  SCARV: a side-channel hardened RISC-V platform
  ☆22Updated 4 years ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆108Updated 3 months ago
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆85Updated 2 months ago
• gatelabdavis / SMTAttack
  SMT Attack
  ☆22Updated 4 years ago
• epfl-vlsc / bitfiltrator
  Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats
  ☆48Updated 2 years ago
• embecosm / ri5cy
  The PULP RI5CY core modified for Verilator modeling and as a GDB server.
  ☆25Updated 7 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆44Updated 2 years ago