Alternatives and similar repositories for SoC_Vulnerability_Benchmarks

Users that are interested in SoC_Vulnerability_Benchmarks are comparing it to the libraries listed below

• ZSusskind / vcd2csv
  Extracts specified data from a VCD file into CSV form
  ☆10Updated 5 years ago
• opentrng / ptrng
  Open-source implementations of reference Physical True Random Number Generators (TRNG or PTRNG) based on ring oscillators.
  ☆13Updated last month
• zero-day-labs / riscv-iopmp
  IOPMP IP
  ☆21Updated 4 months ago
• CommonEvaluationPlatform / CEP
  The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely…
  ☆25Updated last year
• antmicro / rowhammer-tester
  ☆71Updated 2 weeks ago
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆115Updated this week
• agra-uni-bremen / symex-vp
  A concolic testing engine for RISC-V embedded software with support for SystemC peripherals
  ☆26Updated 2 years ago
• proteus-core / proteus
  The SpinalHDL design of the Proteus core, an extensible RISC-V core.
  ☆59Updated 2 weeks ago
• zero-day-labs / riscv-iommu-demo
  RISC-V IOMMU Demo (Linux & Bao)
  ☆23Updated last year
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆92Updated last year
• openhwgroup / cvw-arch-verif
  The purpose of the repo is to support CORE-V Wally architectural verification
  ☆14Updated 3 weeks ago
• lowRISC / ot-sca
  Side-channel analysis setup for OpenTitan
  ☆37Updated 2 weeks ago
• Learning-Chips-Lab / OpenEye
  The Open Source Hardware Accelerator for Efficient Neural Network Inference
  ☆48Updated last week
• Chair-for-Security-Engineering / AES_masked_BRAM
  Designs of first-order SCA-secure hardware implementations of AES encryption/decryptoin dedicated to Xilinx FPGAs (using BRAM)
  ☆16Updated 4 years ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆75Updated last month
• openhwgroup / core-v-polara-apu
  The OpenPiton Platform
  ☆17Updated last year
• ESCristiano / BUSted
  BUSted!!! Microarchitectural Side-Channel Attacks on the MCU Bus Interconnect
  ☆11Updated last year
• comsec-group / mucfi
  Microarchitectural control flow integrity (𝜇CFI) verification checks whether there exists a control or data flow from instruction's ope…
  ☆15Updated 4 months ago
• mit-ll / CEP
  The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…
  ☆66Updated 2 years ago
• comsec-group / encarsia
  ☆25Updated 7 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆168Updated last week
• openhwgroup / cva6-platform
  CVA6-platform is a multicore CVA6 with CV-MESH software and regression platform
  ☆12Updated 2 years ago
• pulp-platform / cheshire-ihp130-o
  ☆58Updated 7 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆43Updated 2 years ago
• aignacio / nox
  RISC-V Nox core
  ☆68Updated 3 months ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆81Updated 8 months ago
• isec-tugraz / coco-alma
  CocoAlma is an execution-aware tool for formal verification of masked implementations
  ☆23Updated last year
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆71Updated last year
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆48Updated 3 years ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆43Updated 2 years ago