socsecresearch / SoC_Vulnerability_BenchmarksLinks
☆11Updated 6 months ago
Alternatives and similar repositories for SoC_Vulnerability_Benchmarks
Users that are interested in SoC_Vulnerability_Benchmarks are comparing it to the libraries listed below
Sorting:
- Extracts specified data from a VCD file into CSV form☆10Updated 5 years ago
- Open-source implementations of reference Physical True Random Number Generators (TRNG or PTRNG) based on ring oscillators.☆13Updated last week
- IOPMP IP☆20Updated 3 months ago
- ☆70Updated 5 months ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely…☆24Updated last year
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆89Updated last year
- The purpose of the repo is to support CORE-V Wally architectural verification☆14Updated last week
- Designs of first-order SCA-secure hardware implementations of AES encryption/decryptoin dedicated to Xilinx FPGAs (using BRAM)☆16Updated 4 years ago
- A concolic testing engine for RISC-V embedded software with support for SystemC peripherals☆26Updated 2 years ago
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆58Updated last week
- CVA6 SDK containing RISC-V tools and Buildroot☆74Updated last week
- HW Design Collateral for Caliptra RoT IP☆113Updated this week
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆48Updated this week
- BUSted!!! Microarchitectural Side-Channel Attacks on the MCU Bus Interconnect☆11Updated last year
- CVA6-platform is a multicore CVA6 with CV-MESH software and regression platform☆12Updated last year
- ☆24Updated 6 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆43Updated 2 years ago
- A demo system for Ibex including debug support and some peripherals☆78Updated 4 months ago
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- Side-channel analysis setup for OpenTitan☆37Updated last month
- A tool for synthesizing Verilog programs☆105Updated 2 months ago
- Test dashboard for verification features in Verilator☆27Updated this week
- Peripheral Component Interconnect (PCI) has taken the Express lane long ago, moving to xGbps SerDes... now for the first time in opensour…☆35Updated this week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆92Updated 2 months ago
- The OpenPiton Platform☆16Updated last year
- A Modular Open-Source Hardware Fuzzing Framework☆36Updated 3 years ago
- ☆57Updated 6 months ago
- SystemVerilog frontend for Yosys☆166Updated this week
- Microarchitectural control flow integrity (𝜇CFI) verification checks whether there exists a control or data flow from instruction's ope…☆15Updated 4 months ago
- Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats☆46Updated 2 years ago