Bucknalla / ip_cores
Verilog IP Cores & Tests
☆13Updated 7 years ago
Alternatives and similar repositories for ip_cores:
Users that are interested in ip_cores are comparing it to the libraries listed below
- ☆15Updated 3 years ago
- development interface mil-std-1553b for system on chip☆21Updated 7 years ago
- File editor for the Xilinx AXI Traffic Generator IP☆16Updated 5 months ago
- Groundhog - Serial ATA Host Bus Adapter☆22Updated 6 years ago
- ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)☆12Updated 6 years ago
- Xilinx IP repository☆13Updated 7 years ago
- Ethernet MAC 10/100 Mbps☆26Updated 3 years ago
- Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language☆16Updated 6 years ago
- ☆20Updated 4 years ago
- USB Full Speed PHY☆44Updated 5 years ago
- ☆29Updated 4 years ago
- IP Cores that can be used within Vivado☆25Updated 3 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆22Updated 7 years ago
- ULPI Link Wrapper (USB Phy Interface)☆25Updated 5 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆36Updated 6 years ago
- Verilog Repository for GIT☆32Updated 4 years ago
- Imaging application using MIPI and DisplayPort to process image☆23Updated 5 years ago
- Testbenches for HDL projects☆15Updated this week
- JESD204b modules in VHDL☆30Updated 6 years ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆33Updated 4 years ago
- UART to AXI Stream interface written in VHDL☆16Updated 2 years ago
- SPI-Flash XIP Interface (Verilog)☆37Updated 3 years ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆18Updated 3 years ago
- Repository containing the DSP gateware cores☆12Updated 7 months ago
- Fixed-point math library with VHDL, Python and MATLAB support☆22Updated 2 months ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 9 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆33Updated 7 years ago
- OscillatorIMP ecosystem FPGA IP sources☆27Updated last month
- Extensible FPGA control platform☆60Updated 2 years ago