Verilog IP Cores & Tests
☆13May 3, 2018Updated 7 years ago
Alternatives and similar repositories for ip_cores
Users that are interested in ip_cores are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Xilinx IP repository☆13May 5, 2018Updated 7 years ago
- IP Cores that can be used within Vivado☆27May 18, 2021Updated 4 years ago
- VHDL Bypass descriptor controller for Xilinx DMA IP for PCIe☆18Oct 23, 2019Updated 6 years ago
- ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)☆13Aug 29, 2018Updated 7 years ago
- IPv4/UDP stack written in VHDL code, for interfacing with an FPGA over Ethernet☆11Jun 2, 2021Updated 4 years ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- IP cores for the FPGA Libre project☆12Aug 7, 2017Updated 8 years ago
- Picorv32 SoC that uses only BRAM, not flash memory☆13Nov 27, 2018Updated 7 years ago
- User Space NVMe Driver (modified for use on Zynq UltraScale+ MPSoC)☆11Sep 26, 2018Updated 7 years ago
- Xilinx Virtual Cable server written in python connecting Xilinx with different JTAG adapters☆11Dec 20, 2013Updated 12 years ago
- ☆20May 8, 2012Updated 13 years ago
- Creation of a AXI Master and Yocto device driver for Zynq, using High Level Synthesis (HLS) techniques.☆13May 28, 2015Updated 10 years ago
- VHDL ieee_proposed library, imported as is. See also https://github.com/FPHDL/fphdl☆12Aug 26, 2016Updated 9 years ago
- Hardware Snappy decompressor☆11Sep 11, 2024Updated last year
- High-througput logic analyzer for FPGA☆16Oct 8, 2020Updated 5 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- ☆12Jul 20, 2022Updated 3 years ago
- SHA-1,SHA-256,SHA-512 Secure Hash Generator written in VHDL(RTL) for FPGA(Xilinx and Altera).☆12Oct 14, 2017Updated 8 years ago
- ☆21Dec 9, 2018Updated 7 years ago
- Repository containing the DSP gateware cores☆14Mar 9, 2026Updated 2 weeks ago
- VHDL Library for implementing common DSP functionality.☆31Oct 5, 2018Updated 7 years ago
- Multi-threaded 32-bit embedded core family.☆24Jul 9, 2012Updated 13 years ago
- OscillatorIMP ecosystem FPGA IP sources☆27Feb 22, 2026Updated last month
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- The official repository of the local FPGA Development Kit.☆19Apr 30, 2019Updated 6 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- A C++ template library for FPGAs on top of Xilinx Vivado HLS☆14Feb 2, 2017Updated 9 years ago
- high level VHDL floating point library for synthesis in fpga☆18Dec 18, 2025Updated 3 months ago
- 通过SPI协议实现FPGA multiboot在线升级功能☆13May 17, 2018Updated 7 years ago
- File editor for the Xilinx AXI Traffic Generator IP☆17Feb 9, 2026Updated last month
- Exploring Shared Virtual Memory Abstractions in OpenCL Tools for FPGAs☆18Dec 7, 2017Updated 8 years ago
- Works in Progress and Experiments for the Innova-2 Flex XCKU15P-based Board☆18Apr 4, 2024Updated last year
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- VHDL package to provide C-like string formatting☆15May 6, 2022Updated 3 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- cryptography ip-cores in vhdl / verilog☆41Feb 20, 2021Updated 5 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆17Mar 14, 2020Updated 6 years ago
- ☆15Dec 21, 2014Updated 11 years ago
- VHDL implementation of carrier phase recovery (CPR) techniques for coherent optical systems☆16Dec 6, 2020Updated 5 years ago
- Blackman-Harris Window functions (3-, 5-, 7-term etc.) from 1K to 64M points based only on LUTs and DSP48s FPGA resources. Main core - CO…☆13Aug 14, 2020Updated 5 years ago
- PCB to breakout 8-lane PCI Express to SATA connectors, for use with FPGAs☆25Sep 17, 2013Updated 12 years ago
- computer hardware system including ps2/vga with tank war game in verilog and mips☆21Oct 21, 2015Updated 10 years ago