vRTLmod modifies Verilator generated RTL simulation code for faul-injection purposes. It transforms source code with the help of LLVM/Clang-Tools and generates a fault injection API.
☆18Mar 28, 2026Updated 2 weeks ago
Alternatives and similar repositories for vrtlmod
Users that are interested in vrtlmod are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Provides a packaged collection of open source EDA tools☆12Apr 14, 2019Updated 7 years ago
- A Formal Verification Framework for Chisel☆19Apr 9, 2024Updated 2 years ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆18Feb 22, 2026Updated last month
- The top repository for the code accompanying our paper "Mind the Gap: Studying the Insecurity of Provably Secure Embedded Trusted Executi…☆16Aug 3, 2022Updated 3 years ago
- understanding of cocotb (In Chinese Only)☆22Jun 10, 2025Updated 10 months ago
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ARCHIE is a QEMU-based architecture-independent fault evaluation tool, that is able to simulate transient and permanent instruction and d…☆33Mar 13, 2026Updated last month
- [IPSN 2024] Lifelong Intelligence Beyond the Edge using Hyperdimensional Computing☆13May 16, 2024Updated last year
- ☆10Nov 8, 2019Updated 6 years ago
- VGA LCD Core (OpenCores)☆15May 22, 2018Updated 7 years ago
- AI Accelerators-SC23-tutorial Repository☆12Nov 12, 2023Updated 2 years ago
- ☆15Mar 27, 2026Updated 2 weeks ago
- A tiny 3-stage RISC-V core written in Chisel.☆16Apr 14, 2023Updated 3 years ago
- SPI Protocol Driver for TI CC1101 based RF communication modules.☆10Oct 30, 2015Updated 10 years ago
- An example of how to create a p2 composite update site during the build☆11Oct 18, 2019Updated 6 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- A Out-of-box PyTorch Scaffold for Neural Network Quantization-Aware-Training (QAT) Research. Website: https://github.com/zhutmost/neuralz…☆25Dec 20, 2022Updated 3 years ago
- ☆18Oct 3, 2024Updated last year
- Minimal startup code + Makefile for building bare-metal C programs for Cortex-M4☆11Jul 26, 2016Updated 9 years ago
- DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction (ASP-DAC 2024)☆13Nov 2, 2023Updated 2 years ago
- There is segmentation fault of VCS which should be fixed.☆44Sep 19, 2023Updated 2 years ago
- ☆20Apr 8, 2026Updated last week
- An implementation of the Sodor 1-Stage RISC-V processor in SpinalHDL.☆14Jun 5, 2019Updated 6 years ago
- A simple AXI4 DMA unit written in SpinalHDL.☆18Apr 18, 2020Updated 5 years ago
- Quickly update a bitstream with new RAM contents☆16Jun 8, 2021Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- This Repo contains SystemC for testBench for AMBA® 3 AHB-Lite Protocol☆13Jul 11, 2018Updated 7 years ago
- ☆13Aug 22, 2022Updated 3 years ago
- ☆43Updated this week
- SystemVerilog & Verilog Module I/O parser and printer☆25Jul 25, 2021Updated 4 years ago
- Digital Waveform Viewer☆17Jan 22, 2024Updated 2 years ago
- ☆17Feb 24, 2025Updated last year
- ☆19Aug 27, 2022Updated 3 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆15Nov 9, 2014Updated 11 years ago
- Pipelined RISC-V CPU☆27Jun 9, 2021Updated 4 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- grep for context, not just text. Local-first CLI for searching documents, notes, memories, and project context.☆24Mar 8, 2026Updated last month
- APB UVC ported to Verilator☆11Nov 19, 2023Updated 2 years ago
- Go client library for OpenProject☆19Nov 22, 2022Updated 3 years ago
- ☆16Dec 4, 2021Updated 4 years ago
- Implementation VexRiscv on ultra96☆13Apr 18, 2022Updated 3 years ago
- ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.☆39Feb 22, 2026Updated last month
- OpenMZ, a security kernel for RISC-V targeting secure coprocessors and secure embedded systems.☆14Jun 26, 2020Updated 5 years ago