☆16Aug 15, 2021Updated 4 years ago
Alternatives and similar repositories for VSD-Physical-Verification-Using-Sky130
Users that are interested in VSD-Physical-Verification-Using-Sky130 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A RRAM addon for the NCSU FreePDK 45nm☆25Jan 10, 2022Updated 4 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆82Sep 17, 2022Updated 3 years ago
- ☆14Sep 29, 2024Updated last year
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆49Dec 6, 2020Updated 5 years ago
- ☆19Jul 12, 2024Updated last year
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- LAYout with Gridded Objects v2☆67Jun 22, 2025Updated 10 months ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆19Jul 21, 2020Updated 5 years ago
- Design of 4KB Static RAM 1.8V (access time <2.5ns) using OpenRAM and Sky130 node☆17Mar 31, 2021Updated 5 years ago
- Lock circuitgraphs using various logic locking techniques☆11May 2, 2023Updated 3 years ago
- QSapecNG☆14Jun 7, 2021Updated 4 years ago
- Space CACD☆11Oct 16, 2019Updated 6 years ago
- A basic implementation of a SAT attack on logic locking.☆13Jun 30, 2021Updated 4 years ago
- Parser for LEF library files☆39Sep 22, 2020Updated 5 years ago
- This repo contains introduction of gm/id method and its application to some OTA design examples.☆19Dec 5, 2023Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Primitives for GF180MCU provided by GlobalFoundries.☆12Jul 6, 2025Updated 9 months ago
- Large language models (LLMs) made easy, EasyLM is a one stop solution for pre-training, finetuning, evaluating and serving LLMs in JAX/Fl…☆11Apr 26, 2023Updated 3 years ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆29Jan 21, 2025Updated last year
- Multi-Objective Reinforcement Learning sandbox☆12Dec 20, 2021Updated 4 years ago
- Repo to help explain the different options users have for packaging.☆19Jun 8, 2022Updated 3 years ago
- Simple OpenGL canvas/event handling library☆14May 7, 2024Updated last year
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆15Apr 11, 2023Updated 3 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆85May 2, 2021Updated 5 years ago
- A synthesizable, five-stage, pipelined 32-bit RISC-V processor (implements the RV32I base ISA)☆13Apr 18, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- KLayout technology files for Skywater SKY130☆44Jul 19, 2023Updated 2 years ago
- FasterCap is a powerful three- and two-dimensional capactiance extraction program.☆37Oct 25, 2019Updated 6 years ago
- This is a Latex template is only for RV College of Engineering students for their report writing in latex.☆19Jan 27, 2026Updated 3 months ago
- Simian Process Oriented Conservative JIT PDES from LANL☆13Dec 12, 2025Updated 4 months ago
- Re-host of ISCAS89 sequential benchmark circuits in higher level verilog (without "DFF")☆17Dec 3, 2021Updated 4 years ago
- A simple dot file / graph generator for Verilog syntax trees.☆23Jul 16, 2016Updated 9 years ago
- Fully defined liberty (std. cells in VLSI) data structure, efficient parser & formatter☆25Feb 24, 2026Updated 2 months ago
- SAT-based ATPG using TG-Pro model☆19Jun 5, 2018Updated 7 years ago
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆71Nov 26, 2025Updated 5 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Code for artificial toy data sets used to evaluate (conditional) invertible neural networks and related methods☆13Feb 11, 2021Updated 5 years ago
- gaw3-20200922 fork with patches to improve remote commands sent from xschem to display waveforms☆17Mar 28, 2025Updated last year
- EM simulation scripts to simulate passive devices on Skywater 130nm open-source process. (Octave interface only for now)☆13Jan 7, 2024Updated 2 years ago
- Galaksija computer for FPGA☆17Jul 6, 2025Updated 9 months ago
- Spiking neural network implementation using Verilog with LIF (Leaky Integrate-and-Fire) neurons☆20Jun 17, 2020Updated 5 years ago
- Sparse Convex Optimization Toolkit (SCOT)☆13Feb 5, 2024Updated 2 years ago
- Minimal vi-like text editor☆18Sep 21, 2019Updated 6 years ago