☆16Aug 15, 2021Updated 4 years ago
Alternatives and similar repositories for VSD-Physical-Verification-Using-Sky130
Users that are interested in VSD-Physical-Verification-Using-Sky130 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆78Sep 17, 2022Updated 3 years ago
- ☆13Sep 29, 2024Updated last year
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆49Dec 6, 2020Updated 5 years ago
- ☆19Jul 12, 2024Updated last year
- LAYout with Gridded Objects v2☆67Jun 22, 2025Updated 9 months ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆18Jul 21, 2020Updated 5 years ago
- Design of 4KB Static RAM 1.8V (access time <2.5ns) using OpenRAM and Sky130 node☆16Mar 31, 2021Updated 4 years ago
- Lock circuitgraphs using various logic locking techniques☆11May 2, 2023Updated 2 years ago
- Tooling to use the Pynq Board somewhat nicely☆13Dec 5, 2022Updated 3 years ago
- QSapecNG☆14Jun 7, 2021Updated 4 years ago
- Space CACD☆11Oct 16, 2019Updated 6 years ago
- Providing examples on how to setup and use xschem, ngspice, and gaw, to do analog IC design☆15Jul 6, 2025Updated 8 months ago
- An implementation of a lexically scoped, referentially transparent, minimal Lisp with some added features☆10Mar 30, 2022Updated 3 years ago
- Parser for LEF library files☆38Sep 22, 2020Updated 5 years ago
- This repo contains introduction of gm/id method and its application to some OTA design examples.☆18Dec 5, 2023Updated 2 years ago
- Primitives for GF180MCU provided by GlobalFoundries.☆12Jul 6, 2025Updated 8 months ago
- React component for draggable, efficiently rendering large lists with react-window☆11Feb 26, 2021Updated 5 years ago
- Large language models (LLMs) made easy, EasyLM is a one stop solution for pre-training, finetuning, evaluating and serving LLMs in JAX/Fl…☆11Apr 26, 2023Updated 2 years ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆29Jan 21, 2025Updated last year
- A binary format for Rust / serde that supports schema evolution☆17Feb 10, 2025Updated last year
- Multi-Objective Reinforcement Learning sandbox☆12Dec 20, 2021Updated 4 years ago
- A home-made stack based language heavily inspired from PostScript☆11Jan 24, 2020Updated 6 years ago
- Simple OpenGL canvas/event handling library☆14May 7, 2024Updated last year
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆15Apr 11, 2023Updated 2 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆82May 2, 2021Updated 4 years ago
- Smart shell that can handle mutliple REPLs☆13Oct 22, 2016Updated 9 years ago
- A synthesizable, five-stage, pipelined 32-bit RISC-V processor (implements the RV32I base ISA)☆12Apr 18, 2024Updated last year
- FasterCap is a powerful three- and two-dimensional capactiance extraction program.☆34Oct 25, 2019Updated 6 years ago
- https://caravel-user-project.readthedocs.io☆230Feb 25, 2025Updated last year
- Node based graph editor for Dear ImGui☆17Jan 2, 2024Updated 2 years ago
- Nova is a programming language with a high level of abstraction. This repository contains nova's bytecode compiler written in C# Using An…☆10Mar 8, 2022Updated 4 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆18Feb 12, 2024Updated 2 years ago
- This is a Latex template is only for RV College of Engineering students for their report writing in latex.☆14Jan 27, 2026Updated last month
- Re-host of ISCAS89 sequential benchmark circuits in higher level verilog (without "DFF")☆16Dec 3, 2021Updated 4 years ago
- Invertible neural network for gravitational wave parameter estimation☆11Nov 22, 2022Updated 3 years ago
- Super Mega Extra Awesome Game Of Life☆14Nov 20, 2022Updated 3 years ago
- SAT-based ATPG using TG-Pro model☆19Jun 5, 2018Updated 7 years ago
- A simple dot file / graph generator for Verilog syntax trees.☆23Jul 16, 2016Updated 9 years ago
- Fully defined liberty (std. cells in VLSI) data structure, efficient parser & formatter☆24Feb 24, 2026Updated last month