acoimbramendes / uart_RTL_to_GDSIILinks
Project of an integrated UART: RTL, Verification, Physical Implementation (Innovus) and GDSII.
☆11Updated 4 years ago
Alternatives and similar repositories for uart_RTL_to_GDSII
Users that are interested in uart_RTL_to_GDSII are comparing it to the libraries listed below
Sorting:
- A verilog FPGA Interface for AXI4_Lite from Slave side☆10Updated 5 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆65Updated 11 months ago
- A verilog implementation for Network-on-Chip☆74Updated 7 years ago
- A Spiking Neuron Network Project in Verilog Implementation☆23Updated 7 years ago
- ☆56Updated 2 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- ☆34Updated 6 years ago
- AXI Interconnect☆50Updated 3 years ago
- Verification IP for APB protocol☆66Updated 4 years ago
- General Purpose AXI Direct Memory Access☆53Updated last year
- AXI总线连接器☆100Updated 5 years ago
- AXI4 BFM in Verilog☆32Updated 8 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation inc…☆20Updated last year
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆19Updated last year
- ☆67Updated 9 years ago
- AXI DMA 32 / 64 bits☆115Updated 11 years ago
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- Mirror of william_william/uvm-mcdf on Gitee☆24Updated 2 years ago
- ☆20Updated 2 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆58Updated last year
- PCIE 5.0 Graduation project (Verification Team)☆78Updated last year
- Simple AMBA VIP, Include axi/ahb/apb☆26Updated last year
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例,并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆25Updated 2 years ago
- AMBA bus generator including AXI, AHB, and APB☆105Updated 3 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆34Updated 2 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆37Updated 8 years ago
- UART design in SV and verification using UVM and SV☆44Updated 5 years ago
- This is the repository for the IEEE version of the book☆66Updated 4 years ago
- AXI4 and AXI4-Lite interface definitions☆93Updated 4 years ago