Project of an integrated UART: RTL, Verification, Physical Implementation (Innovus) and GDSII.
☆16May 28, 2021Updated 4 years ago
Alternatives and similar repositories for uart_RTL_to_GDSII
Users that are interested in uart_RTL_to_GDSII are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- DTMF Receiver: Logic Synthesis and Physical Design using genus and innovus in 90nm process node☆16Dec 1, 2023Updated 2 years ago
- reference block design for the ASAP7nm library in Cadence Innovus☆64Jun 25, 2024Updated last year
- soc integration script and integration smoke script☆24Sep 12, 2022Updated 3 years ago
- TCL, verilog and shell scripts used while learning Cadence genus, innovus and tempus tools.☆17Oct 24, 2021Updated 4 years ago
- A Bitcoin mining ASIC☆12Dec 2, 2022Updated 3 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Cell Layout Generation for DTCO/STCO Exploration Toolkit☆26May 24, 2025Updated last year
- cadence flow for genus and innovus with UPF added.☆17Jul 3, 2021Updated 4 years ago
- Re-host of ISCAS89 sequential benchmark circuits in higher level verilog (without "DFF")☆17Dec 3, 2021Updated 4 years ago
- ☆17Apr 7, 2022Updated 4 years ago
- A simple spidergon network-on-chip with wormhole switching feature☆12Mar 22, 2021Updated 5 years ago
- Python bindings for openlava☆10Oct 24, 2019Updated 6 years ago
- This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.☆12Sep 6, 2023Updated 2 years ago
- General Purpose IO with APB4 interface☆16May 10, 2024Updated 2 years ago
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆12Jan 8, 2022Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆22Sep 26, 2025Updated 8 months ago
- Small and simple, primitive SoC with GPU, CPU, RAM, GPIO☆14Dec 29, 2016Updated 9 years ago
- 一些小的python脚本☆13Nov 13, 2025Updated 6 months ago
- ☆13Nov 13, 2022Updated 3 years ago
- 🇨🇳 SWCC — Democratic Centralism Multi-Agent Orchestration for Claude Code (民主集中制多智能体编排)☆63Mar 13, 2026Updated 2 months ago
- risc-v 单周期和流水线cpu设计, 基于miniRV-1指令集,语言verilog☆11Feb 23, 2023Updated 3 years ago
- Memory Compiler Tutorial☆14Oct 7, 2020Updated 5 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- Web interface for job information☆14Jul 23, 2020Updated 5 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Various low power labs using sky130☆13Sep 3, 2021Updated 4 years ago
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆32Jan 17, 2020Updated 6 years ago
- ☆12Mar 10, 2023Updated 3 years ago
- Coarse Grained Reconfigurable Arrays with Chisel3☆12Jul 1, 2024Updated last year
- ☆10Nov 4, 2022Updated 3 years ago
- Design and simulate a simplified ARM single-cycle processor using SystemVerilog.☆10Sep 13, 2019Updated 6 years ago
- HDL components to build a customized Wishbone crossbar switch☆15May 30, 2019Updated 6 years ago
- 国科大高等数字集成电路分析与设计课程2022fall☆31Dec 13, 2022Updated 3 years ago
- A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).☆32Jun 13, 2015Updated 10 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Hardware Formal Verification☆17Aug 10, 2020Updated 5 years ago
- Innovus backend scripts☆13Jun 20, 2022Updated 3 years ago
- 2048 Game created via Verilog, loaded on an FPGA board and VGA monitor.☆12Mar 25, 2022Updated 4 years ago
- FPGA创新设计大赛全国二等奖,Multi-functional Game Console Based on RISC-V.(基于紫光FPGA的RSIC V多功能游戏机)☆11Aug 16, 2024Updated last year
- ☆14Mar 4, 2020Updated 6 years ago
- A Direct Memory Access Controller (DMAC) with AHB-lite bus interface☆17Oct 6, 2024Updated last year
- Pan's 1st Gen RISC-V SoC, contains a 12T multicycle RISC-V32ia core, with an EMIF-like simple bus☆16Oct 21, 2020Updated 5 years ago