Alternatives and similar repositories for riscv-cpu

Users that are interested in riscv-cpu are comparing it to the libraries listed below

• airin711 / Verilog-caches
  Various caches written in Verilog-HDL
  ☆126Updated 10 years ago
• tom01h / zero-riscy
  zero-riscy CPU Core
  ☆17Updated 7 years ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆128Updated 4 years ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆155Updated 10 months ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆74Updated 2 months ago
• A-T-Kristensen / simple-alu-uvm
  This is full tutorial of UVM (Universal Verification Methodology) for a simple ALU unit
  ☆25Updated 7 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆175Updated 3 weeks ago
• RPTU-EIS / upec-boom-verification-suite
  This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks ba…
  ☆19Updated 2 years ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆76Updated 7 years ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆103Updated 3 months ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆68Updated last year
• riscv-ovpsim / imperas-riscv-tests
  ☆187Updated last year
• woshiyyya / RISCV-CPU
  Write a CPU from scratch! (5-stage pipeline & 2-way-cache)
  ☆20Updated 6 years ago
• prasadp4009 / 2-way-Set-Associative-Cache-Controller
  Synthesizable and Parameterized Cache Controller in Verilog
  ☆45Updated 2 years ago
• pulp-platform / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆19Updated 2 months ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆89Updated last year
• jasonlin316 / RISC-V-CPU
  A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
  ☆135Updated 5 years ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆191Updated 3 years ago
• Lampro-Mellon / LM-RISCV-DV
  An Open-Source Design and Verification Environment for RISC-V
  ☆83Updated 4 years ago
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆145Updated 5 years ago
• cassuto / nano-cpu32k
  Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.
  ☆56Updated last year
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆76Updated last week
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆217Updated 5 years ago
• chipsalliance / uvm-verilator
  ☆97Updated 2 years ago
• Evensgn / RISC-V-CPU
  RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
  ☆306Updated 7 years ago
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆105Updated 4 months ago
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆137Updated 2 years ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆110Updated last year
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆227Updated this week