Pipelined RISC-V CPU
☆27Jun 9, 2021Updated 5 years ago
Alternatives and similar repositories for riscv-cpu
Users that are interested in riscv-cpu are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RISC-V multi cycle CPU. Project of Computer Organization (THU 2020)☆17Nov 30, 2022Updated 3 years ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 4 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11May 29, 2021Updated 5 years ago
- Re-host of ISCAS89 sequential benchmark circuits in higher level verilog (without "DFF")☆17Dec 3, 2021Updated 4 years ago
- ☆14Sep 27, 2022Updated 3 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆149Dec 2, 2019Updated 6 years ago
- Implementation of RISC-V RV32I☆30Aug 30, 2022Updated 3 years ago
- RISC-V-5 stage pipelined in verilog☆10Jul 24, 2020Updated 5 years ago
- This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog☆30Feb 19, 2025Updated last year
- RISC-V SOC (both single and pipeline) implemented in Verilog. Passed all test codes provided by TA.☆21Jun 3, 2023Updated 3 years ago
- RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.☆366Jan 12, 2018Updated 8 years ago
- 伴伴學 RISC-V RV32I Architecture CPU☆31Sep 23, 2022Updated 3 years ago
- Integer Multiplier Generator for Verilog☆25Jul 4, 2025Updated 11 months ago
- ☆13Jun 12, 2024Updated 2 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Verilog projects for simulation and logic synthesis (Icarus Verilog, YOSYS)☆22Apr 28, 2021Updated 5 years ago
- Writing a hypervisor in Rust☆11Apr 1, 2025Updated last year
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- Beti Elektronik - ddApp -10 FPGA Uygulamaları (Eğitim) Seti☆13Dec 31, 2024Updated last year
- The top repository for the code accompanying our paper "Mind the Gap: Studying the Insecurity of Provably Secure Embedded Trusted Executi…☆16Aug 3, 2022Updated 3 years ago
- A small and simple rv32i core written in Verilog☆18Jul 29, 2022Updated 3 years ago
- A light-weight hardware oriented synchronous stream cipher.☆12Mar 19, 2022Updated 4 years ago
- Open-source implementations of reference Physical True Random Number Generators (TRNG or PTRNG) based on ring oscillators.☆17Mar 26, 2026Updated 2 months ago
- fpga verilog risc-v rv32i cpu☆15Apr 18, 2023Updated 3 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- This project aims to implement a pipelined processor based on the RISC-V instruction set architecture (ISA) using Vivado and Verilog. The…☆17Aug 22, 2024Updated last year
- vRTLmod modifies Verilator generated RTL simulation code for faul-injection purposes. It transforms source code with the help of LLVM/C…☆20Mar 28, 2026Updated 2 months ago
- 64-bit MISC Architecture CPU☆13Dec 13, 2016Updated 9 years ago
- ☆12Dec 10, 2025Updated 6 months ago
- Trying to learn Wishbone by implementing few master/slave devices☆13Jan 7, 2019Updated 7 years ago
- An open silicon CHERIoT Ibex microcontroller chip☆18May 23, 2025Updated last year
- MIPS 57条指令五级流水线cpu (verilog实现+详细注释)☆11Jan 11, 2022Updated 4 years ago
- DTMF Receiver: Logic Synthesis and Physical Design using genus and innovus in 90nm process node☆18Dec 1, 2023Updated 2 years ago
- 北京理工大学大四小学期计算机组成原理部分☆10Sep 24, 2020Updated 5 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- risc-v-myth-workshop-august-Redbeard358 created by GitHub Classroom☆18Sep 15, 2020Updated 5 years ago
- Verilog CAN controller that is compatible to the SJA 1000.☆17Apr 17, 2021Updated 5 years ago
- Setup guides for Raptor Talos II Secure Workstation based on IBM's Power9 CPU.☆15Sep 7, 2025Updated 9 months ago
- Study notes for ARM Assembly Language: Fundamentals and Techniques, Second Edition William Hohl, Christopher Hinds☆15Jun 17, 2017Updated 8 years ago
- Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo☆15Jul 31, 2024Updated last year
- APB Timer Unit☆14Oct 30, 2025Updated 7 months ago
- Implementation of CORDIC Algorithms Using Verilog☆26Apr 26, 2021Updated 5 years ago