Pipelined RISC-V CPU
☆27Jun 9, 2021Updated 4 years ago
Alternatives and similar repositories for riscv-cpu
Users that are interested in riscv-cpu are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RISC-V multi cycle CPU. Project of Computer Organization (THU 2020)☆17Nov 30, 2022Updated 3 years ago
- A synthesizable, five-stage, pipelined 32-bit RISC-V processor (implements the RV32I base ISA)☆13Apr 18, 2024Updated 2 years ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 4 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11May 29, 2021Updated 4 years ago
- Re-host of ISCAS89 sequential benchmark circuits in higher level verilog (without "DFF")☆17Dec 3, 2021Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Write a CPU from scratch! (5-stage pipeline & 2-way-cache)☆21Jul 18, 2019Updated 6 years ago
- ☆14Sep 27, 2022Updated 3 years ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆148Dec 2, 2019Updated 6 years ago
- Implementation of RISC-V RV32I☆30Aug 30, 2022Updated 3 years ago
- RISC-V-5 stage pipelined in verilog☆10Jul 24, 2020Updated 5 years ago
- This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog☆29Feb 19, 2025Updated last year
- RISC-V SOC (both single and pipeline) implemented in Verilog. Passed all test codes provided by TA.☆21Jun 3, 2023Updated 2 years ago
- RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.☆364Jan 12, 2018Updated 8 years ago
- 伴伴學 RISC-V RV32I Architecture CPU☆31Sep 23, 2022Updated 3 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- DEsign 16-bit ALU using Verilog☆10Feb 13, 2016Updated 10 years ago
- Single-cycle MIPS processor in Verilog HDL.☆10May 1, 2020Updated 6 years ago
- Integer Multiplier Generator for Verilog☆25Jul 4, 2025Updated 10 months ago
- ☆13Jun 12, 2024Updated last year
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- FIFO implementation with different clock domains for read and write.☆14Aug 17, 2021Updated 4 years ago
- Verilog projects for simulation and logic synthesis (Icarus Verilog, YOSYS)☆22Apr 28, 2021Updated 5 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- Beti Elektronik - ddApp -10 FPGA Uygulamaları (Eğitim) Seti☆13Dec 31, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A light-weight hardware oriented synchronous stream cipher.☆12Mar 19, 2022Updated 4 years ago
- AVR CPU Core Implementation in Verilog HDL.☆15Oct 28, 2018Updated 7 years ago
- Open-source implementations of reference Physical True Random Number Generators (TRNG or PTRNG) based on ring oscillators.☆16Mar 26, 2026Updated last month
- fpga verilog risc-v rv32i cpu☆15Apr 18, 2023Updated 3 years ago
- vRTLmod modifies Verilator generated RTL simulation code for faul-injection purposes. It transforms source code with the help of LLVM/C…☆18Mar 28, 2026Updated last month
- 64-bit MISC Architecture CPU☆13Dec 13, 2016Updated 9 years ago
- ☆12Dec 10, 2025Updated 4 months ago
- An open silicon CHERIoT Ibex microcontroller chip☆18May 23, 2025Updated 11 months ago
- MIPS 57条指令五级流水线cpu (verilog实现+详细注释)☆11Jan 11, 2022Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- DTMF Receiver: Logic Synthesis and Physical Design using genus and innovus in 90nm process node☆15Dec 1, 2023Updated 2 years ago
- risc-v-myth-workshop-august-Redbeard358 created by GitHub Classroom☆17Sep 15, 2020Updated 5 years ago
- Verilog CAN controller that is compatible to the SJA 1000.☆16Apr 17, 2021Updated 5 years ago
- Setup guides for Raptor Talos II Secure Workstation based on IBM's Power9 CPU.☆15Sep 7, 2025Updated 7 months ago
- OpenPiton Design Benchmark☆28Mar 6, 2023Updated 3 years ago
- Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo☆14Jul 31, 2024Updated last year
- APB Timer Unit☆14Oct 30, 2025Updated 6 months ago