sdasgup3 / parallel-processor-design
Super scalar Processor design
☆21Updated 10 years ago
Related projects ⓘ
Alternatives and complementary repositories for parallel-processor-design
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 2 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆52Updated 4 years ago
- Useful utilities for BAR projects☆30Updated 10 months ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…☆22Updated 5 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated last year
- SCARV: a side-channel hardened RISC-V platform☆24Updated last year
- ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set☆4Updated 2 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆59Updated 3 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆20Updated 3 weeks ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆89Updated 3 years ago
- SoftCPU/SoC engine-V☆54Updated last year
- Parallel Array of Simple Cores. Multicore processor.☆92Updated 5 years ago
- Processing Unit with RISCV-32 / RISCV-64 / RISCV-128☆19Updated 3 weeks ago
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆26Updated this week
- Experiments with fixed function renderers and Chisel HDL☆58Updated 5 years ago
- Wishbone to ARM AMBA 4 AXI☆13Updated 5 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 4 years ago
- Yet Another RISC-V Implementation☆85Updated 2 months ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆30Updated 3 years ago
- FGPU is a soft GPU architecture general purpose computing☆56Updated 4 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆72Updated 5 years ago
- ☆21Updated 7 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆79Updated 5 years ago
- SPIR-V fragment shader GPU core based on RISC-V☆36Updated 3 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆39Updated 4 years ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆14Updated 5 years ago
- ☆15Updated 3 years ago