sdasgup3 / parallel-processor-designLinks
Super scalar Processor design
☆21Updated 10 years ago
Alternatives and similar repositories for parallel-processor-design
Users that are interested in parallel-processor-design are comparing it to the libraries listed below
Sorting:
- Hamming ECC Encoder and Decoder to protect memories☆33Updated 4 months ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆54Updated 4 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 3 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆67Updated last year
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Updated 2 weeks ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- Processing Unit with RISCV-32 / RISCV-64 / RISCV-128☆20Updated 2 weeks ago
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆29Updated 12 years ago
- Verilog projects for simulation and logic synthesis (Icarus Verilog, YOSYS)☆22Updated 4 years ago
- SoftCPU/SoC engine-V☆54Updated 2 months ago
- ☆33Updated 2 years ago
- ☆58Updated 4 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆42Updated 2 years ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆98Updated 3 years ago
- SPIR-V fragment shader GPU core based on RISC-V☆39Updated 4 years ago
- Xilinx Unisim Library in Verilog☆78Updated 4 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 7 months ago
- Another tiny RISC-V implementation☆55Updated 3 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- pulp_soc is the core building component of PULP based SoCs☆80Updated 2 months ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated 10 months ago
- Experiments with fixed function renderers and Chisel HDL☆59Updated 6 years ago
- Basic floating-point components for RISC-V processors☆65Updated 5 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆32Updated last year
- RISC-V Core Local Interrupt Controller (CLINT)☆26Updated last year
- This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.☆18Updated 2 years ago
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- A RISC-V processor☆15Updated 6 years ago