sjduan / LeHDCLinks
☆15Updated 6 months ago
Alternatives and similar repositories for LeHDC
Users that are interested in LeHDC are comparing it to the libraries listed below
Sorting:
- [TCAD'24] This repository contains the source code for the paper "FireFly v2: Advancing Hardware Support for High-Performance Spiking Neu…☆20Updated last year
- LoAS: Fully Temporal-Parallel Dataflow for Dual-Sparse Spiking Neural Networks, MICRO 2024.☆13Updated 6 months ago
- Open-source of MSD framework☆16Updated 2 years ago
- Collection of kernel accelerators optimised for LLM execution☆23Updated 5 months ago
- C++ code for HLS FPGA implementation of transformer☆18Updated last year
- ☆18Updated last year
- The official implementation of HPCA 2025 paper, Prosperity: Accelerating Spiking Neural Networks via Product Sparsity☆36Updated last month
- ☆29Updated 5 months ago
- bitfusion verilog implementation☆12Updated 3 years ago
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆16Updated 2 years ago
- [DATE 2025] Official implementation and dataset of AIrchitect v2: Learning the Hardware Accelerator Design Space through Unified Represen…☆16Updated 8 months ago
- From Pytorch model to C++ for Vitis HLS☆17Updated last week
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆19Updated 6 years ago
- Accelerate multihead attention transformer model using HLS for FPGA☆12Updated last year
- [ASP-DAC 2025] "NeuronQuant: Accurate and Efficient Post-Training Quantization for Spiking Neural Networks" Official Implementation☆12Updated 6 months ago
- ☆18Updated 2 years ago
- ☆19Updated 2 years ago
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆13Updated 2 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆38Updated 6 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆13Updated 4 years ago
- Framework for radix encoded SNN on FPGA☆14Updated 3 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆16Updated last year
- Attentionlego☆12Updated last year
- [TVLSI'23] This repository contains the source code for the paper "FireFly: A High-Throughput Hardware Accelerator for Spiking Neural Net…☆20Updated last year
- ☆31Updated last week
- ☆51Updated 2 months ago
- Torch2Chip (MLSys, 2024)☆54Updated 5 months ago
- ☆21Updated 2 years ago
- ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales - HDL source code and documentation.☆86Updated 3 years ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆22Updated last year