Implementation of the SHA256 Algorithm in Verilog
☆39Jan 2, 2012Updated 14 years ago
Alternatives and similar repositories for verilog-sha256
Users that are interested in verilog-sha256 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog based FPGA Design of SHA256 Simulated on ModelSim☆24May 18, 2018Updated 8 years ago
- Implementation of SHA256 Hasher with UART Transceiver in Verilog. Designed to run on Altera's DE2 FPGA Development Board.☆16Oct 16, 2018Updated 8 years ago
- SHA-256 IP core for ZedBoard (Zynq SoC)☆31Jun 22, 2018Updated 8 years ago
- Verilog implementation of the SHA-512 hash function.☆47Jan 17, 2026Updated 9 months ago
- Verilog Code for a JPEG Decoder☆34Mar 7, 2018Updated 8 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- A implement of Chinese SHA(SM3) on FPGA from SHU ACTION team☆10Oct 9, 2019Updated 7 years ago
- Partial Verilog implimentation of a WiMAX OFDM Phy☆19May 28, 2012Updated 14 years ago
- SM4加密解密算法Verilog代码实现☆13Jun 5, 2024Updated 2 years ago
- Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog☆42Jun 4, 2017Updated 9 years ago
- Description of Chinese SM3 Hash algorithm with Verilog HDL☆56Aug 5, 2018Updated 8 years ago
- AES加密解密算法的Verilog实现☆71Jan 17, 2016Updated 10 years ago
- Simple demo showing how to use the ping pong FIFO☆17May 2, 2016Updated 10 years ago
- Design a new OFDM synchronization algorithm, and implement it with both Matlab and Verilog.☆21Feb 8, 2017Updated 9 years ago
- FIPS 202 compliant SHA-3 core in Verilog☆26Oct 8, 2020Updated 6 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- DDR4 Simulation Project in System Verilog☆47Aug 18, 2014Updated 12 years ago
- FPGA implementation of Chinese SM4 encryption algorithm.☆57Mar 11, 2018Updated 8 years ago
- Implementation of the PCIe physical layer☆64Jul 11, 2025Updated last year
- Verilog Implementation of SM4 s-box☆22Jun 24, 2019Updated 7 years ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated 2 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆31Apr 25, 2016Updated 10 years ago
- FFT algorithm coded in Verilog. Designed to run on a Xillinx Spartan 6 FPGA board.☆15Jul 19, 2012Updated 14 years ago
- Cryptonight Monero Verilog code for ASIC☆20Mar 29, 2018Updated 8 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆12Aug 22, 2021Updated 5 years ago
- Identifies ASL Hand Gesture for numbers using image processing in verilog☆15May 3, 2012Updated 14 years ago
- RFID tag and tester in Verilog☆41Apr 4, 2013Updated 13 years ago
- FMCW Radar verilog project☆36Jun 15, 2020Updated 6 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆33Nov 6, 2018Updated 8 years ago
- A Voila-Jones face detector hardware implementation☆33Nov 29, 2018Updated 7 years ago
- MT29F128G based NAND flash controller☆10Jun 17, 2021Updated 5 years ago
- Wraps the NVDLA project for Chipyard integration☆24Sep 2, 2025Updated last year
- axi video dma ip in verilog☆11Aug 22, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Implementation of ECC on FPGA-Zynq7000 SoC☆21Jul 12, 2019Updated 7 years ago
- Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.☆17Oct 8, 2020Updated 6 years ago
- ☆20Jun 18, 2022Updated 4 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆42Oct 16, 2017Updated 9 years ago
- H.264/AVC Baseline Decoder☆16Jul 17, 2014Updated 12 years ago
- Clock Data Recovery | 時鐘數據恢復☆12Aug 9, 2020Updated 6 years ago