alexforencich / verilog-lfsrLinks
Fully parametrizable combinatorial parallel LFSR/CRC module
☆154Updated 5 months ago
Alternatives and similar repositories for verilog-lfsr
Users that are interested in verilog-lfsr are comparing it to the libraries listed below
Sorting:
- Verilog digital signal processing components☆150Updated 2 years ago
- RTL Verilog library for various DSP modules☆89Updated 3 years ago
- AHB3-Lite Interconnect☆90Updated last year
- PCIE 5.0 Graduation project (Verification Team)☆79Updated last year
- Verilog based BCH encoder/decoder☆123Updated 2 years ago
- SDRAM controller with AXI4 interface☆96Updated 6 years ago
- UART -> AXI Bridge☆63Updated 4 years ago
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- DDR2 memory controller written in Verilog☆77Updated 13 years ago
- ☆163Updated 2 years ago
- Fixed Point Math Library for Verilog☆141Updated 11 years ago
- AXI interface modules for Cocotb☆276Updated last year
- Examples and reference for System Verilog Assertions☆87Updated 8 years ago
- Generic FIFO implementation with optional FWFT☆59Updated 5 years ago
- AMBA bus generator including AXI, AHB, and APB☆105Updated 4 years ago
- ☆70Updated 3 years ago
- Control and Status Register map generator for HDL projects☆122Updated 3 months ago
- Altera Advanced Synthesis Cookbook 11.0☆107Updated 2 years ago
- A collection of phase locked loop (PLL) related projects☆108Updated last year
- This is the repository for the IEEE version of the book☆68Updated 4 years ago
- round robin arbiter☆75Updated 11 years ago
- Pre-packaged testbenching tools and reusable bus interfaces for cocotb☆65Updated 3 weeks ago
- System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers☆76Updated 6 years ago
- Ethernet 10GE MAC☆45Updated 11 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆69Updated 4 years ago
- SystemVerilog testbench for an Ethernet 10GE MAC core☆45Updated 9 years ago
- 10G Low Latency Ethernet☆59Updated 2 years ago
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆132Updated 5 years ago
- Interface Protocol in Verilog☆50Updated 6 years ago
- UVM 1.2 port to Python☆253Updated 6 months ago