alexforencich / corundum
Open source FPGA-based NIC and platform for in-network compute
☆61Updated 4 months ago
Alternatives and similar repositories for corundum:
Users that are interested in corundum are comparing it to the libraries listed below
- Verilog Content Addressable Memory Module☆104Updated 3 years ago
- Ethernet interface modules for Cocotb☆60Updated last year
- Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC☆62Updated 8 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- Gigabit MAC + UDP/TCP/IP offload Engine☆31Updated 5 years ago
- Ethernet 10GE MAC☆45Updated 10 years ago
- Ethernet switch implementation written in Verilog☆44Updated last year
- Ethernet MAC 10/100 Mbps☆79Updated 5 years ago
- ☆56Updated 2 years ago
- Verilog Ethernet components for FPGA implementation☆19Updated last year
- A simple DDR3 memory controller☆54Updated 2 years ago
- Pre-packaged testbenching tools and reusable bus interfaces for cocotb☆62Updated 5 months ago
- ☆16Updated 3 years ago
- Extensible FPGA control platform☆59Updated last year
- Repository gathering basic modules for CDC purpose☆53Updated 5 years ago
- Hardware Assisted IEEE 1588 IP Core☆27Updated 10 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆64Updated 4 months ago
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆92Updated this week
- Verilog Ethernet Switch (layer 2)☆41Updated last year
- UART models for cocotb☆26Updated 2 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆42Updated last year
- PCI express simulation framework for Cocotb☆154Updated last year
- 10G Low Latency Ethernet☆48Updated last year
- ☆53Updated 4 years ago
- Simple hash table on Verilog (SystemVerilog)☆48Updated 8 years ago
- NVMe Controller featuring Hardware Acceleration☆83Updated 3 years ago
- Groundhog - Serial ATA Host Bus Adapter☆22Updated 6 years ago
- I2C models for cocotb☆31Updated this week
- Verilog network module. Models network traffic from pcap to AXI-Stream☆23Updated 3 years ago
- UART -> AXI Bridge☆60Updated 3 years ago