VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW ta…
☆19Jul 21, 2020Updated 6 years ago
Alternatives and similar repositories for vsdflow
Users that are interested in vsdflow are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆15Dec 2, 2021Updated 4 years ago
- An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop…☆16Jul 22, 2020Updated 6 years ago
- ☆25Oct 3, 2025Updated last year
- ☆17Sep 19, 2022Updated 4 years ago
- This project is based on Digital VLSI Testing and Testability. The netlist is given as input, the code performs Dominance fault collapsin…☆11Nov 16, 2021Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- This project has files needed to design and characterise flipflop☆21Jun 3, 2019Updated 7 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆20Oct 18, 2023Updated 3 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆52Dec 6, 2020Updated 5 years ago
- ☆22Aug 4, 2022Updated 4 years ago
- ☆13Mar 25, 2022Updated 4 years ago
- This script builds openlane and all its dependencies on an Ubuntu (only) System.☆26Aug 12, 2022Updated 4 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆37Dec 30, 2022Updated 3 years ago
- Cache-accel: FPGA Accelerated Multi-Core Cache Simulator☆14Mar 12, 2022Updated 4 years ago
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆32Jun 4, 2024Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆13Apr 22, 2021Updated 5 years ago
- Verilog HDL code and documentation for pipelined RISC-V processors designed as a minor project by a team of 4. Includes testbench files, …☆11Nov 23, 2023Updated 2 years ago
- Arbitrary Cell Generator enables parametrized grid-free circuit layout creation☆17Jun 1, 2020Updated 6 years ago
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆170Apr 1, 2026Updated 6 months ago
- ☆36Apr 22, 2026Updated 6 months ago
- This repository is created for conducting RISC-V 5-day workshops☆24Jul 29, 2020Updated 6 years ago
- ☆16May 11, 2022Updated 4 years ago
- WaveEye is an AXI4-Lite protocol root cause analysis tool that explains why a violation must occur by identifying missing inter-FSM depen…☆13Mar 30, 2026Updated 6 months ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- A extremely size-optimized RV32I soft processor for FPGA.☆27Jun 19, 2018Updated 8 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆33Jun 27, 2022Updated 4 years ago
- ☆11Jul 9, 2025Updated last year
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆91May 2, 2021Updated 5 years ago
- FIR and LMS filter implementations in FPGAs☆15Nov 18, 2019Updated 6 years ago
- 64-bit RISC-V processor☆18Nov 30, 2022Updated 3 years ago
- Implementation of a low-pass FIR filter in Verilog HDL.☆12Apr 12, 2024Updated 2 years ago
- SRAM Design using OpenSource Applications☆26Jul 16, 2021Updated 5 years ago
- Projects created for the Vim course at FMI☆20Sep 25, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A caravan equipped with API for creating bus protocols in Chisel with ease.☆14Jan 15, 2026Updated 9 months ago
- ☆39Jul 11, 2022Updated 4 years ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆15Aug 26, 2024Updated 2 years ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆19Updated this week
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆99Sep 17, 2022Updated 4 years ago
- Various low power labs using sky130☆13Sep 3, 2021Updated 5 years ago
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆18Oct 16, 2021Updated 5 years ago