Complete ASIC Design of UART Interface with Baud Rate Selection :- RTL to GDS2
☆13Sep 3, 2019Updated 6 years ago
Alternatives and similar repositories for UART-RTL-Physical-Design
Users that are interested in UART-RTL-Physical-Design are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- OpenROAD Agent. This repository contain the model to train and testing the model using EDA Corpus dataset.☆29Jul 24, 2025Updated 11 months ago
- This repository contains all the information included in the beginner SoC/physical design using open-source EDA tools organized by VLSI S…☆14Mar 7, 2021Updated 5 years ago
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- Simple RISC-V RV32I CPU in VHDL for use in FPGA Designs☆19Sep 2, 2019Updated 6 years ago
- Implementing Different Adder Structures in Verilog☆76Sep 3, 2019Updated 6 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- This project was done as a part of Beginner VLSI/SoC Physical design using open-source EDA Tools workshop.☆13Nov 23, 2020Updated 5 years ago
- A project to perform the VLSI Physical Design Flow steps of partitioning, floorplan, placement and routing.☆13Jun 9, 2021Updated 5 years ago
- This is a Latex template is only for RV College of Engineering students for their report writing in latex.☆26May 29, 2026Updated last month
- NTHU CS6135 VLSI實體設計自動化☆12Mar 12, 2022Updated 4 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆34Jun 12, 2023Updated 3 years ago
- ☆86Dec 16, 2025Updated 6 months ago
- SystemVerilog examples and projects☆21Jun 10, 2025Updated last year
- UW reference flow for Free45PDK and The OpenROAD Project☆13Jun 5, 2020Updated 6 years ago
- RISC-V 32-bit core for MCCI Catena 4710☆10Jul 31, 2019Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆10Jan 30, 2017Updated 9 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆17Sep 23, 2020Updated 5 years ago
- Open SoC Debug Hardware Reference Implementation☆16Jul 15, 2019Updated 6 years ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 4 years ago
- A deep learning based bioinformatics project on epigenetics in Type 2 Diabetes.☆17Mar 25, 2023Updated 3 years ago
- Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools☆129May 14, 2022Updated 4 years ago
- Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher☆17Feb 27, 2024Updated 2 years ago
- Hardware design project of the FIX and TCP/IP offload engines on FPGA, containing HDL codes and Python codes for testing.☆22Dec 11, 2023Updated 2 years ago
- Routing Visualization for Physical Design☆20Dec 24, 2018Updated 7 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- This repository contains an example of the connection between an UVM Testbench and a Python reference model.☆12Nov 6, 2019Updated 6 years ago
- Practical example from the SPIE short course "Data Analytics and Machine Learning in Semiconductor Manufacturing: Applications for Physic…☆23Feb 25, 2018Updated 8 years ago
- This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specificatio…☆35Jan 23, 2024Updated 2 years ago
- RTL Synthesis for Fast Arithmetic circuits like Booth encoded Multipliers, Carry Save Adders, Fixed-Point and Floating-Point conversions,…☆22Nov 26, 2018Updated 7 years ago
- This is a collection of the built in libraries of the VHDPlus IDE toghether with examples. Commits will be featured in the IDE with futur…☆21Feb 27, 2024Updated 2 years ago
- NTHU CS6135 VLSI Physical Design Automation (2022 Fall)☆19Jan 20, 2023Updated 3 years ago
- a cyclic redundancy check(one kind of Error Correcting Code) software(MATLAB) and hardware(Verilog HDL) implementation.☆11Dec 14, 2019Updated 6 years ago
- 7 track standard cells for GF180MCU provided by GlobalFoundries.☆29Dec 1, 2022Updated 3 years ago
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆18Dec 12, 2025Updated 6 months ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Open-sourced utilities for initial flow setup, calibration, and other user functions for OpenROAD project☆21Aug 20, 2019Updated 6 years ago
- A ZipCPU SoC for the Nexys Video board supporting video functionality☆20Nov 13, 2024Updated last year
- A project implementing the CORDIC algorithm for computing cosines and sines using fixed-point decimals in Verilog code（使用定点小数在 verilog 代码…☆11Aug 19, 2023Updated 2 years ago
- DDR3 controller for nMigen (WIP)☆14Dec 25, 2023Updated 2 years ago
- SKY130 ReRAM and examples (SkyWater Provided)☆45Apr 20, 2022Updated 4 years ago
- 基于arm cortex-m0内核的xillinx fpga sopc工程项目☆13May 28, 2019Updated 7 years ago
- This repo contains the skeleton scripts for running a full RTL2GDS flow using Cadence tools, as demonstrated in the Full RTL2GDS Demo pre…☆79Oct 18, 2025Updated 8 months ago