Devipriya1921 / vsdserializer_v1Links
☆15Updated last year
Alternatives and similar repositories for vsdserializer_v1
Users that are interested in vsdserializer_v1 are comparing it to the libraries listed below
Sorting:
- Open Source PHY v2☆31Updated last year
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆33Updated 4 years ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆31Updated 4 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆75Updated 5 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆68Updated 9 months ago
- Complete tutorial code.☆22Updated last year
- ☆43Updated 3 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆27Updated last year
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 4 years ago
- ☆38Updated 3 years ago
- Test dashboard for verification features in Verilator☆28Updated this week
- ☆56Updated 2 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated 11 months ago
- Open source process design kit for 28nm open process☆67Updated last year
- An open source PDK using TIGFET 10nm devices.☆54Updated 2 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆82Updated 4 years ago
- 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.☆122Updated 2 weeks ago
- ☆44Updated 5 years ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆28Updated 4 years ago
- A place to keep my synthesizable verilog examples.☆47Updated 7 months ago
- The memory model was leveraged from micron.☆24Updated 7 years ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated last year
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆49Updated 3 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆162Updated 2 weeks ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- SoCRocket - Core Repository☆38Updated 8 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- Introductory course into static timing analysis (STA).☆99Updated 4 months ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆63Updated 4 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 4 months ago