jimwang99 / parser-for-chip-designLinks
A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).
☆33Updated 10 years ago
Alternatives and similar repositories for parser-for-chip-design
Users that are interested in parser-for-chip-design are comparing it to the libraries listed below
Sorting:
- Python-based Verilog Parser (currently Netlist only)☆54Updated 8 years ago
- Automatic generation of real number models from analog circuits☆45Updated last year
- Mirror of Synopsys's Liberty parser library☆24Updated 7 years ago
- This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download…☆25Updated 2 years ago
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆35Updated 3 years ago
- Circuit release of the MAGICAL project☆39Updated 5 years ago
- repository for a bandgap voltage reference in SKY130 technology☆41Updated 2 years ago
- BAG2 workspace for fake PDK (cds_ff_mpt)☆59Updated 5 years ago
- Python Tool for UVM Testbench Generation☆54Updated last year
- Parametric layout generator for digital, analog and mixed-signal integrated circuits☆61Updated last week
- ☆20Updated 3 years ago
- GDSII File Parsing, IC Layout Analysis, and Parameter Extraction☆127Updated 2 years ago
- LAYout with Gridded Objects v2☆65Updated 4 months ago
- This is a tutorial on standard digital design flow☆79Updated 4 years ago
- ☆33Updated 5 years ago
- EDA physical synthesis optimization kit☆62Updated last year
- Intel's Analog Detailed Router☆39Updated 6 years ago
- SystemVerilog RTL Linter for YoSys☆21Updated 11 months ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- A Standalone Structural Verilog Parser☆99Updated 3 years ago
- ideas and eda software for vlsi design☆50Updated last week
- ☆43Updated 3 years ago
- Physical Design Flow from RTL to GDS using Opensource tools.☆112Updated 4 years ago
- Python port of Prof. Boris Murmann's gm/ID Starter Kit☆54Updated 8 years ago
- FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already ins…☆103Updated last year
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆79Updated 4 years ago
- ☆44Updated 5 years ago
- This repo contains introduction of gm/id method and its application to some OTA design examples.☆18Updated last year
- This repo is created to include illustrative examples on object oriented design pattern in SV☆60Updated 2 years ago
- Running Python code in SystemVerilog☆70Updated 4 months ago