A simple tool to demonstrate the physical design steps of VLSI Design Flow.
☆11Dec 13, 2020Updated 5 years ago
Alternatives and similar repositories for VLSI_Physical_Design_Tool
Users that are interested in VLSI_Physical_Design_Tool are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Courseworks of CS6165 VLSI Physical Design Automation, NTHU.☆49Jan 23, 2021Updated 5 years ago
- Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"☆27Dec 9, 2018Updated 7 years ago
- NTHU CS6135 VLSI Physical Design Automation (2022 Fall)☆19Jan 20, 2023Updated 3 years ago
- Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.☆35May 20, 2020Updated 6 years ago
- Examples of the TCL Scripts for different purposes and for VLSI Physical Design are provided here for your reference☆38Dec 30, 2022Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- This repository contains all the information included in the beginner SoC/physical design using open-source EDA tools organized by VLSI S…☆14Mar 7, 2021Updated 5 years ago
- Complete ASIC Design of UART Interface with Baud Rate Selection :- RTL to GDS2☆13Sep 3, 2019Updated 6 years ago
- MSC bootloader for STM32F103 (Blue Pill etc)☆13Apr 9, 2022Updated 4 years ago
- Semiconductor Packaging Fundamentals☆36May 19, 2025Updated last year
- Introductory course for Perl 5 through examples, geared towards VLSI engineers☆52Oct 1, 2020Updated 5 years ago
- This project was done as a part of Beginner VLSI/SoC Physical design using open-source EDA Tools workshop.☆14Nov 23, 2020Updated 5 years ago
- NTHU CS6135 VLSI實體設計自動化☆11Mar 12, 2022Updated 4 years ago
- Routing Visualization for Physical Design☆20Dec 24, 2018Updated 7 years ago
- This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specificatio…☆36Jan 23, 2024Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Senior Design☆12Jan 26, 2025Updated last year
- Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Syno…☆14Jun 9, 2021Updated 5 years ago
- This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other detai…☆47Mar 22, 2019Updated 7 years ago
- Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format☆13Feb 13, 2020Updated 6 years ago
- Spiking Neural Network Accelerator☆15May 18, 2022Updated 4 years ago
- Example of a full DC synthesis script for a simple design☆14Feb 25, 2019Updated 7 years ago
- 32-bit RISC-V microcontroller☆12Sep 11, 2021Updated 4 years ago
- RISC-V-5 stage pipelined in verilog☆10Jul 24, 2020Updated 6 years ago
- IEEE Executive project for the year 2021-2022☆11Nov 22, 2022Updated 3 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆19Jul 21, 2020Updated 6 years ago
- The Repository contains the code of various Digital Circuits☆13Aug 7, 2023Updated 2 years ago
- This is a hardware implementation of exact multiply accumulator for 32-bit posit number with es=2☆17Jan 27, 2018Updated 8 years ago
- Personal mirror for adv_debug_sys☆11Aug 23, 2011Updated 14 years ago
- ☆11Jan 25, 2023Updated 3 years ago
- OpenROAD Agent. This repository contain the model to train and testing the model using EDA Corpus dataset.☆32Jul 24, 2025Updated last year
- Tool for parsing an integrated circuit test file from STIL to the particular file format of a Teradyne tester.☆16May 17, 2018Updated 8 years ago
- UW reference flow for Free45PDK and The OpenROAD Project☆14Jun 5, 2020Updated 6 years ago
- Brilliantly Radical Artificially Intelligent Neural Machine☆18Dec 28, 2017Updated 8 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Incremental Timing-Driven Placement, problem C of ICCAD contest 2015☆16Sep 28, 2017Updated 8 years ago
- A Convolutional Neural Network (CNN) hardware accelerator for image recognition☆15Jul 14, 2019Updated 7 years ago
- A pipelined brainfuck softcore in Verilog☆20Aug 5, 2014Updated 11 years ago
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆18Jan 28, 2022Updated 4 years ago
- Real-time Audio Processing through FIR filters on Basys-3 FPGA and Pmod I2S2☆18Feb 1, 2023Updated 3 years ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆19Jan 25, 2022Updated 4 years ago
- TCL, verilog and shell scripts used while learning Cadence genus, innovus and tempus tools.☆17Oct 24, 2021Updated 4 years ago