This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out
☆58Jan 23, 2024Updated 2 years ago
Alternatives and similar repositories for VLSI-ASIC-Design-Flow
Users that are interested in VLSI-ASIC-Design-Flow are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This project offers an immersive tutorial experienced within the context of the Advanced Physical Design, focusing on the utilization of …☆43Sep 21, 2023Updated 3 years ago
- This project was done as a part of Beginner VLSI/SoC Physical design using open-source EDA Tools workshop.☆14Nov 23, 2020Updated 5 years ago
- This repository contains all the information included in the beginner SoC/physical design using open-source EDA tools organized by VLSI S…☆14Mar 7, 2021Updated 5 years ago
- Examples of the TCL Scripts for different purposes and for VLSI Physical Design are provided here for your reference☆40Dec 30, 2022Updated 3 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆56Jan 4, 2022Updated 4 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)☆34Nov 25, 2024Updated last year
- ☆16Apr 8, 2023Updated 3 years ago
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- This project is about building a Clocked Comparator to be used in a 4-bit Flash ADC & minimize the ADC Figure of Merit given by FoM = Pow…☆18Sep 12, 2023Updated 3 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆142Feb 22, 2024Updated 2 years ago
- This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A c…☆13Jul 8, 2019Updated 7 years ago
- This project is about building a high FOM 2.4 GHz LNA for Bluetooth Low-Energy (BLE) Standards, using 45nm CMOS technology.☆18Mar 17, 2019Updated 7 years ago
- This script builds openlane and all its dependencies on an Ubuntu (only) System.☆26Aug 12, 2022Updated 4 years ago
- The project involves the design of a 4X4 (16-bit) SRAM Memory Array using Cadence Virtuoso☆71Mar 21, 2024Updated 2 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆68Mar 13, 2025Updated last year
- This repository provides an automated shell script to set up a Verilator + UVM-based workflow using the [RTL2UVM](https://github.com/rpja…☆21Oct 21, 2025Updated last year
- ☆14Apr 13, 2025Updated last year
- 9-bit SAR in skywater 130 nm☆21Jan 15, 2025Updated last year
- LibreCores Web Site☆36Jan 7, 2023Updated 3 years ago
- An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop…☆16Jul 22, 2020Updated 6 years ago
- This project shows the design of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using h…☆26May 2, 2025Updated last year
- An open-source 32-bit RISC-V soft-core processor☆48Updated this week
- VHDL package to provide C-like string formatting☆15May 6, 2022Updated 4 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆70Updated this week
- This projects contains Veriolg code and timing analysis of a asynchronous FIFO. The README.md document is maintained, which explains ever…☆51Jul 29, 2024Updated 2 years ago
- The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a c…☆580Updated this week
- Hardware Accelerators on FPGA for Computer Vision Applications☆16Dec 16, 2025Updated 10 months ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆100Sep 17, 2022Updated 4 years ago
- This project shows how to model a 4-bit flash ADC and a 4-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs …☆23Apr 20, 2019Updated 7 years ago
- Two Stage CMOS Operational Amplifier IP Design using Skywater 130nm Technology☆27Jul 23, 2022Updated 4 years ago
- Memory Compiler Tutorial☆15Oct 7, 2020Updated 6 years ago
- repository for a bandgap voltage reference in SKY130 technology☆44Jan 20, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A fullstack web framework for dart☆14Oct 12, 2026Updated 3 weeks ago
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆35Feb 21, 2019Updated 7 years ago
- A ROHD-based framework for connectivity and assembly of hardware designs.☆14Sep 9, 2026Updated last month
- IHP Open source SG13G2 Tape Out on May 2025 [Testfield T588]☆15Apr 27, 2026Updated 6 months ago
- ☆14Oct 5, 2024Updated 2 years ago
- TCL Script automating the frontend of ASIC design☆11Jun 21, 2023Updated 3 years ago
- This repository is a detailed summary of RTL design using sky130 PDK organized by VLSI System Design☆28Jun 1, 2025Updated last year