☆18Dec 13, 2022Updated 3 years ago
Alternatives and similar repositories for Physical-Verification-using-synopsys-40nm
Users that are interested in Physical-Verification-using-synopsys-40nm are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆16May 23, 2024Updated 2 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Synopsys tools.☆16Jun 28, 2025Updated last year
- RTL to GDS via Cadence Tools☆20May 17, 2022Updated 4 years ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆21Aug 19, 2024Updated 2 years ago
- Repository for VSD-IAT Workshop: Physical Verification using SKY130☆10Aug 15, 2021Updated 5 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- This repository contains all the materials related to the basic MOSFET theory, CMOS technology, circuit and layout design, and basic PDK …☆15Dec 15, 2023Updated 2 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆34Apr 29, 2024Updated 2 years ago
- Linter for SystemVerilog Assertions (SVA). Following the philosophy of BYOL - Build Your Own Linter, SVALint is an example of ho users ca…☆22Aug 23, 2026Updated 2 months ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆140Feb 22, 2024Updated 2 years ago
- Complete installation flow of yosys, OpenSTA and OpenROAD for RTL Verification, Synthesis, Timing Analysis, Power Analysis & GDSII layout…☆27Jul 21, 2025Updated last year
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.☆33Feb 11, 2024Updated 2 years ago
- Implementation of both, sequential and 5-stage pipelined x86 64-bit processor in Verilog, designed to handle data dependencies like load-…☆14Jul 11, 2023Updated 3 years ago
- ☆18Apr 7, 2022Updated 4 years ago
- 9 track standard cells for GF180MCU provided by GlobalFoundries.☆19Dec 5, 2022Updated 3 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Notes I made on RTL design and verification. Currently has verilog, system verilog and formal verification notes☆11Sep 23, 2023Updated 3 years ago
- Artifacts for the SCVP lecture☆12Nov 17, 2021Updated 4 years ago
- Simple UVM testbench development using the uvmtb_template files☆27Jan 16, 2025Updated last year
- Low Power VLSI Design Concepts & Interview Questions for Top Semiconductor MNCs☆12Jan 12, 2023Updated 3 years ago
- AT89C52单片机实验程序:发光二极管的亮灭、多个发光二极管分组循环交替亮灭、外部中断控制数码管循环显示0~9、定时器控制发光二极管的亮灭+简单输出连续矩形脉冲。☆11Mar 20, 2022Updated 4 years ago
- A backend API for Quiz inspired by 16 personalities☆11Oct 5, 2021Updated 5 years ago
- This course explains the basics of Tcl scripting language, which is embedded in almost all EDA tools and can be used to automate many ope…☆21Jul 11, 2026Updated 3 months ago
- Code implementing the system of nonlinear equations that describes nonlinearities in silicon microring modulators.☆10Apr 5, 2021Updated 5 years ago
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆12Jan 8, 2022Updated 4 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Some beginner projects using verilog HDL, along with some documentation on basic syntax☆14Jun 13, 2021Updated 5 years ago
- Scrabble in C++, done for an OOPS course project☆15May 19, 2021Updated 5 years ago
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆18Oct 16, 2021Updated 5 years ago
- Personal mirror for adv_debug_sys☆11Aug 23, 2011Updated 15 years ago
- ☆32Oct 3, 2022Updated 4 years ago
- The Verilog model for SRAM IS61WV102416 chip with timings☆10Mar 14, 2015Updated 11 years ago
- Misc utility FPGA cores☆13Mar 21, 2023Updated 3 years ago
- Memory Compiler Tutorial☆15Oct 7, 2020Updated 6 years ago
- Repository for the Advanced Electronics Laboratory course (MFN1324) at University of Torino, Physics Department☆13Jun 4, 2026Updated 4 months ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Tiny ImageNet Classification Exercise with PyTorch☆16Aug 21, 2021Updated 5 years ago
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- RISC-V compliant Timer IP☆14May 10, 2024Updated 2 years ago
- A Convolutional Neural Network (CNN) hardware accelerator for image recognition☆16Jul 14, 2019Updated 7 years ago
- ☆20Sep 16, 2022Updated 4 years ago
- Coarse Grained Reconfigurable Arrays with Chisel3☆11Jul 1, 2024Updated 2 years ago
- A Y86-64 processor implemented using Verilog☆17Aug 21, 2021Updated 5 years ago