aasthadave9 / Advanced-Physical-Design-Using-OpenLANE-Sky130Links
This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an opensource RTL2GDS flow using OpenLANE and opensource PDK provided by Google/SkyWater130
☆21Updated 4 years ago
Alternatives and similar repositories for Advanced-Physical-Design-Using-OpenLANE-Sky130
Users that are interested in Advanced-Physical-Design-Using-OpenLANE-Sky130 are comparing it to the libraries listed below
Sorting:
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆44Updated 3 years ago
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆25Updated last year
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆98Updated last year
- This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…☆11Updated 3 years ago
- This repo provide an index of VLSI content creators and their materials☆162Updated last year
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆26Updated 2 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆18Updated 2 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆67Updated 3 years ago
- ☆117Updated 2 years ago
- ☆15Updated 2 years ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆15Updated last year
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆14Updated 4 years ago
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆39Updated 3 months ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆82Updated 3 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆81Updated 4 years ago
- Introductory course into static timing analysis (STA).☆99Updated 5 months ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆103Updated 2 years ago
- Curriculum for a university course to teach chip design using open source EDA tools☆127Updated 2 years ago
- ☆170Updated 3 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆38Updated 3 years ago
- ☆52Updated 4 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆64Updated last year
- Static Timing Analysis Full Course☆63Updated 2 years ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆164Updated 2 years ago
- ☆18Updated last year
- ☆14Updated 3 years ago
- Architectural design of data router in verilog☆31Updated 6 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆46Updated 5 years ago
- RTL to GDS via Cadence Tools☆16Updated 3 years ago
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆30Updated last year