aasthadave9 / Advanced-Physical-Design-Using-OpenLANE-Sky130Links
This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an opensource RTL2GDS flow using OpenLANE and opensource PDK provided by Google/SkyWater130
☆15Updated 3 years ago
Alternatives and similar repositories for Advanced-Physical-Design-Using-OpenLANE-Sky130
Users that are interested in Advanced-Physical-Design-Using-OpenLANE-Sky130 are comparing it to the libraries listed below
Sorting:
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆38Updated 3 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- ☆30Updated last year
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆19Updated 2 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆42Updated 3 years ago
- General Purpose AXI Direct Memory Access☆50Updated last year
- Implementing Different Adder Structures in Verilog☆70Updated 5 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆44Updated 3 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆62Updated 2 years ago
- ☆41Updated 3 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆27Updated 3 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆70Updated 4 years ago
- Xilinx AXI VIP example of use☆40Updated 4 years ago
- SystemVerilog RTL Linter for YoSys☆20Updated 6 months ago
- ☆12Updated 2 months ago
- 5 Day TCL begginer to advanced training workshop by VSD☆17Updated last year
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆70Updated 4 years ago
- ☆17Updated 2 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆59Updated last year
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆16Updated 4 years ago
- Introductory course into static timing analysis (STA).☆94Updated last month
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 5 months ago
- DMA Hardware Description with Verilog☆14Updated 5 years ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆25Updated 3 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆30Updated last week
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆42Updated last year
- The memory model was leveraged from micron.☆22Updated 7 years ago
- APB Logic☆18Updated 6 months ago
- This repository aims to capture the works done in 5-day workshop of Adavance Physical Design using OpenLANE/SkyWater130. The workshop hel…☆22Updated 3 years ago
- Static Timing Analysis Full Course☆56Updated 2 years ago