Ashwin-Rajesh / Verilog_projects
Some beginner projects using verilog HDL, along with some documentation on basic syntax
☆11Updated 3 years ago
Alternatives and similar repositories for Verilog_projects:
Users that are interested in Verilog_projects are comparing it to the libraries listed below
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆23Updated 10 months ago
- Design a median filter for a Generic RGB image.☆14Updated 6 years ago
- ☆17Updated 2 years ago
- Implementing Different Adder Structures in Verilog☆65Updated 5 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- DMA Hardware Description with Verilog☆14Updated 5 years ago
- Hamming ECC Encoder and Decoder to protect memories☆32Updated 2 months ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆23Updated last year
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆44Updated 3 years ago
- Cache Controller for a multi-level Cache memory using four-way set-associative mapping with write-back, no-write allocate and LRU policy.…☆9Updated 4 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆26Updated 3 years ago
- This repository contains all the information studied and created during the [Advanced Physical Design Using OpenLANE / SKY130](https://ww…☆17Updated 2 years ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆28Updated 3 years ago
- FFT algorithm for fpga☆19Updated 3 years ago
- IEEE Executive project for the year 2021-2022☆9Updated 2 years ago
- Complete tutorial code.☆19Updated 11 months ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆14Updated 2 years ago
- This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop☆35Updated 3 years ago
- System Verilog BootCamp☆23Updated 3 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆30Updated last year
- ☆12Updated 9 months ago
- APB UVC ported to Verilator☆11Updated last year
- This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an op…☆15Updated 3 years ago
- System Verilog using Functional Verification☆10Updated last year
- Design and UVM-TB of RISC -V Microprocessor☆17Updated 10 months ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- SystemVerilog examples and projects☆17Updated 6 years ago
- ☆21Updated 6 months ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆41Updated 3 years ago